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參數資料
| 型號： | ADM690AARN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | Microprocessor Supervisory Circuits |
| 中文描述： | 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數： | 6/8頁 |
| 文件大小： | 327K |
| 代理商： | ADM690AARN |
ADM690A/ADM692A/ADM802L/M/ADM805L/M
–6–
REV. 0
Table I. Input and Output Status in Battery Backup Mode
Signal
Status
V
OUT
V
OUT
is connected to V
BATT
via an internal
PMOS switch.
Logic low.
Logic high (ADM805L, ADM805M). The open
circuit output voltage is equal to V
OUT
.
The power fail comparator is disabled
Logic low.
The watchdog timer is disabled
RESET
RESET
PFI
PFO
WDI
Power Fail Comparator
The power fail comparator is an independent comparator
that may be used to monitor the input power supply. The
comparator’s inverting input is internally connected to a 1.25
V reference voltage. The noninverting input is available at the
PFI input. This input may be used to monitor the input power
supply via a resistive divider network. When the voltage on the
PFI input drops below 1.25 V, the comparator output (
PFO
)
goes low indicating a power failure. For early warning of power
failure the comparator may be used to monitor the preregulator
input simply by choosing an appropriate resistive divider
network. The
PFO
output can be used to interrupt the
processor so that a shutdown procedure is implemented before
the power is lost.
1.25V
POWER FAIL
OUTPUT
(PFO)
POWER
FAIL
INPUT
INPUT
POWER
R1
R2
Figure 9. Power Fail Comparator
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is non-
inverting, hysteresis can be added simply by connecting a
resistor between the
PFO
output and the PFI input as shown in
Figure 10. When
PFO
is low, resistor R3 sinks current from the
summing junction at the PFI pin. When
PFO
is high, resistor
R3 sources current into the PFI summing junction. This results
in differing trip levels for the comparator. Further noise
immunity may be achieved by connecting a capacitor between
PFI and GND.
1.25V
(PFO)
INPUT
POWER
R1
R2
PFI
R3
TO
μP NMI
5V
PFO
0V
0V
V
L
V
H
V
IN
V
H
= 1.25 1+R2
×
R3
V
L
= 125+R1
1.25 –
CC
–1.25
R2
R3
V
MID
= 1.25
R1+R2
R2
Figure 10. Adding Hysteresis to the Power Fail
Comparator
TYPICAL APPLICATIONS
Figure 11 shows a typical power monitoring, battery backup
application. V
OUT
powers the CMOS RAM. Under normal
operating conditions with V
CC
present, V
OUT
is internally
connected to V
CC
. If a power failure occurs, V
CC
will decay and
V
OUT
will be switched to V
BATT
thereby maintaining power for
the CMOS RAM. A
RESET
pulse is also generated when V
CC
falls below the reset threshold.
CMOS RAM
POWER
μP RESET
μP NMI
I/O LINE
μP SYSTEM
V
CC
μP POWER
V
OUT
RESET
PFO
WDI
GND
V
BATT
PFI
UNREGULATED
DC
R1
R2
+5V
BATTERY
+
Figure 11. Typical Application Circuit
The watchdog timer input (WDI) monitors an I/O line from the
μ
P system. This line must be toggled once every 1.6 seconds to
verify correct software execution. Failure to toggle the line
indicates that the
μ
P system is not correctly executing its
program and may be tied up in an endless loop. If this happens,
a reset pulse is generated to initialize the processor.
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