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參數資料
| 型號： | ADM690SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | Microprocessor Supervisory Circuits |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, CDIP8 |
| 封裝： | CERDIP-8 |
| 文件頁數： | 7/16頁 |
| 文件大小： | 199K |
| 代理商： | ADM690SQ |
ADM690–ADM695
REV. A
–7–
T able I. ADM691, ADM693, ADM695 Reset Pulse Width and Watchdog T imeout Selections
Watchdog T imeout Period
Reset Active Period
Immediately
After Reset
OSC SE L
OSC IN
Normal
ADM691/ADM693
ADM695
Low
Low
Floating or High
Floating or High
External Clock Input
External Capacitor
Low
Floating or High
1024 CLK S
260 ms
×
C/47 pF
100 ms
1.6 s
4096 CLK S
1.04 s
×
C/47 pF
1.6 s
1.6 s
512 CLK S
130 ms
×
C/47 pF
50 ms
50 ms
2048 CLK S
520 ms
×
C/47 pF
200 ms
200 ms
NOT E
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. T he nominal
internal oscillator frequency is 10.24 kHz. T he nominal oscillator frequency with external capacitor is: F
OSC
(Hz) = 184,000/C (pF).
T he watchdog timeout period is fixed at 1.6 seconds, and the
reset pulse width is fixed at 50 ms on the ADM690/ADM692.
On the ADM694 the watchdog timeout period is also 1.6 sec-
onds but the reset pulse width is fixed at 200 ms. T he ADM691/
ADM693/ADM695 allow these times to be adjusted as shown
in T able I. Figure 4 shows the various oscillator configurations
which can be used to adjust the reset pulse width and watchdog
timeout period.
T he internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; while
with it connected low, the 100 ms timeout period is selected. In
either case, immediately after a reset, the timeout period is 1.6
seconds. T his gives the microprocessor time to reinitialize the
system. If OSC IN is low, then the 100 ms watchdog period be-
comes effective after the first transition of WDI. T he software
should be written such that the I/O port driving WDI is left in
its power-up reset state until the initialization routines are com-
pleted and the microprocessor is able to toggle WDI at the mini-
mum watchdog timeout period of 70 ms.
Watchdog Output (WDO)
T he Watchdog Output
WDO
(ADM691/ADM693/ADM695)
provides a status output which goes low if the watchdog timer
“times out” and remains low until set high by the next transition
on the Watchdog Input.
WDO
is also set high when V
CC
goes
below the reset threshold.
OSC IN
OSC SEL
ADM691
ADM693
ADM695
CLOCK
0 TO 250kHz
8
7
Figure 4a. External Clock Source
OSC IN
OSC SEL
ADM691
ADM693
ADM695
8
7
C
OSC
Figure 4b. External Capacitor
OSC IN
OSC SEL
ADM691
ADM693
ADM695
8
7
NC
NC
Figure 4c. Internal Oscillator (1.6 Second Watchdog)
OSC IN
OSC SEL
ADM691
ADM693
ADM695
8
7
NC
Figure 4d. Internal Oscillator (100 ms Watchdog)
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