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參數資料
| 型號： | ADM691AARW |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | IC SW OFF-LINE 46W/79W TO220-7 |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數： | 9/12頁 |
| 文件大小： | 337K |
| 代理商： | ADM691AARW |
ADM691A/ADM693A/ADM800L/M
–9–
REV. 0
7
OSC SEL
OSC IN
8
ADM69_A
ADM800_
C
OSC
Figure 18d. Internal Oscillator (100 ms Watchdog)
WDI
WDO
t
1
RESET
t
1
= RESET TIME.
t
2
= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD.
t
3
= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET.
t
1
t
1
t
2
t
3
Figure 19. Watchdog Timing
CE Gating and RAM Write Protection
All products include memory protection circuitry which ensures
the integrity of data in memory by preventing write operations
when V
CC
is at an invalid level. There are two additional pins,
CE
IN
and
CE
OUT
, that control the Chip Enable or Write inputs
of CMOS RAM. When V
CC
is present,
CE
OUT
is a buffered rep-
lica of
CE
IN
, with a 5 ns propagation delay. When V
CC
falls be-
low the reset voltage threshold, an internal gate forces
CE
OUT
high, independent of
CE
IN
.
CE
OUT
typically drives the CE, CS, or Write input of battery
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V
CC
is at an in-
valid level. Similar protection of EEPROMs can be achieved by
using the
CE
OUT
to drive the Store or Write inputs of an
EEPROM, EAROM, or NOVRAM.
Power Fail Warning Comparator
An additional comparator is provided for early warning of fail-
ure in the microprocessor’s power supply. The Power Fail Input
(PFI) is compared to an internal +1.25 V reference. The Power
Fail Output (
PFO
) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider that
senses either the unregulated dc input to the system’s 5 V regu-
lator or the regulated 5 V output. The voltage divider ratio can
be chosen such that the voltage at PFI falls below 1.25 V several
milliseconds before the +5 V power supply falls below the reset
threshold.
PFO
is normally used to interrupt the microprocessor
so that data can be stored in RAM and the shut- down proce-
dure executed before power is lost.
R2
PFO
1.25V
POWER
FAIL
INPUT
POWER
FAIL
OUTPUT
R1
INPUT
POWER
Figure 20. Power Fail Comparator
Table III. Input and Output Status in Battery Backup Mode
Signal
Status
V
BATT
V
OUT
Supply Current is <1
μ
A.
V
OUT
is connected to V
BATT
via an internal
PMOS switch.
Switchover comparator monitors V
CC
for
active switchover.
0 V.
Logic High. The open circuit voltage is equal
to V
OUT
.
Logic Low.
OSC IN is ignored.
OSC SEL is ignored.
The Power Fail Comparator remains active in
the battery-backup mode for V
CC
≥
V
BATT
–1.2 V. With V
CC
lower than this, PFO is
forced low.
The Power Fail Comparator remains active in
the battery-backup mode for V
CC
≥
V
BATT
–1.2 V. With V
CC
lower than this, PFO is
forced low.
WDI is ignored.
Logic High. The open circuit voltage is equal
to V
OUT
.
High Impedance.
Logic High. The open circuit voltage is equal
to V
OUT
.
Logic Low.
High Impedance.
V
CC
GND
BATT ON
LOW LINE
OSC IN
OSC SEL
PFI
PFO
WDI
CE
OUT
CE
IN
WDO
RESET
RESET
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