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參數(shù)資料
| 型號： | ADM800MAN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | Microprocessor Supervisory Circuits |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 337K |
| 代理商： | ADM800MAN |
ADM691A/ADM693A/ADM800L/M
–7–
REV. 0
10
0%
100
90
400ms
1V
Figure 14.
RESET
Output Voltage vs. Supply
10
0%
100
90
10μs
1V
Figure 15.
RESET
Response Time
POWER FAIL
RESET
OUTPUT
RESET
is an active low output that provides a reset signal to the
Microprocessor whenever V
CC
is at an invalid level. When V
CC
falls below the reset threshold, the
RESET
output is forced
low. The reset voltage threshold is 4.65 V (ADM691A/
ADM800L) or 4.4 V (ADM693A/ADM800M).
On power-up
RESET
will remain low for 200 milliseconds after
V
CC
rises above the appropriate reset threshold. This allows time
for the power supply and microprocessor to stabilize. On power-
down, the
RESET
output remains low with V
CC
as low as 1 V.
This ensures that the microprocessor is held in a stable shut-
down condition. If
RESET
is required to be low for voltages be-
low 1 V, this may be achieved by connecting a pull-down resistor
on the
RESET
line. The resistor will help maintain
RESET
low
down to V
CC
= 0 V. Note that this is only necessary if V
BATT
is
below 2 V. With battery voltages
≥
2 V
RESET
will function cor-
rectly with V
CC
from 0 V to +5.5 V.
This reset active time is adjustable by using an external oscillator
or by connecting an external capacitor to the OSC IN pin. Refer
to Table II.
The guaranteed minimum and maximum thresholds of the
ADM691A/ADM800L are 4.5 V and 4.75 V, while the guaran-
teed thresholds of the ADM693A/ADM800M are 4.25 V and
4.5 V. The ADM691A/ADM800L is therefore compatible with
5 V supplies with a +10%, –5% tolerance while the ADM693A/
ADM800M is compatible with 5 V
±
10% supplies.
In addition to
RESET
an active high RESET output is provided.
This is the complement of
RESET
and is useful for processors
requiring an active high RESET signal.
Watchdog Timer Reset
The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, a reset pulse is generated. The watch-
dog timeout period may be configured for either a fixed “short”
100 ms or a “l(fā)ong” 1.6 second timeout period or for an adjust-
able timeout period. Note that even if the short timeout period
is selected, the first time out immediately following a reset is
1.6 sec. This is to allow additional time for the microprocessor
to regain control following a reset.
The watchdog timer is restarted at the end of reset, whether the
reset was caused by lack of activity on WDI or by V
CC
falling be-
low the reset threshold.
The normal (short) timeout period becomes effective following
the first transition of WDI after reset has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be is-
sued after each timeout period (1.6 seconds). The watchdog
monitor can be deactivated by floating the Watchdog Input
(WDI). If floating, an internal resistor network biases WDI to
around 1.6 V.
COUTPUT
CONTROL
V
BATT
V
CC
CE
IN
OSC IN
OSC SEL
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
1
VOLTAGE DETECTOR = 4.4V (ADM693A/ADM800M)
ADM691A/ADM693A
ADM800L/ADM800M
1.25V
WATCHDOG
TRANSITION DETECTOR
WATCHDOG
TIMER
TIMEBASE
GRESET &
4.65V
1
BATT ON
LOW LINE
V
OUT
CE
OUT
RESET
RESET
WATCHDOG
OUTPUT (
WDO
)
POWER FAIL
OUTPUT (
PFO
)
Figure 16. Functional Block Diagram
Watchdog Output (
WDO
)
The Watchdog Output
WDO
provides a status output that goes
low if the watchdog timer “times out” and remains low until set
high by the next transition on the watchdog input.
WDO
is also
set high when V
CC
goes below the reset threshold. If WDI re-
mains high or low indefinitely,
RESET
and RESET will gener-
ate 200 ms pulses every 1.6 sec.
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