
ADM8830
–4–
PIN CONFIGURATIONS
LFCSP
15 C4–
14 C2+
13 C2–
12 C3+
11 C3–
V
1
VOUT 2
LDO_IN 3
+5VOUT 4
+5VIN 5
2
L
O
S
S
B
C
+
1
1
1
1
PIN 1
ADM8830
TOP VIEW
TSSOP
TOP VIEW
(Not to Scale)
ADM8830
C1–
GND
C1+
–10VOUT
V
CC
C4+
VOUT
C4–
LDO_IN
C2+
+5VOUT
C2–
+5VIN
C3+
LDO_ON/
OFF
C3–
SHDN
+15VOUT
SCAN/
BLANK
CLKIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIN FUNCTION DESCRIPTIONS
Pin Number
TSSOP LFCSP Mnemonic Function
1, 2 19, 20 C1–, C1+ External capacitor C1 is connected between these pins. A 2.2 μF capacitor is recommended.
3 1 V
CC
Positive Supply Voltage Input. Connect this pin to 3 V supply with a 2.2 μF decoupling capacitor.
4 2 VOUT Voltage Doubler Output. This is derived by doubling the 3 V supply. A 2.2 μF capacitor to
ground is required on this pin.
5 3 LDO_IN Voltage Regulator Input. The user has the option to bypass this circuit using the
LDO_ON/
OFF
pin.
6 4 +5VOUT +5.1 V Output Pin. This is derived by doubling and regulating the 3 V supply. A 2.2 μF ca-
pacitor to ground is required on this pin to stabilize the regulator.
7 5 +5VIN +5.1 V Input Pin. This is the input to the voltage tripler and doubler inverter charge pump
circuits.
8 6 LDO_ON/
OFF
Control Logic Input. 3 V CMOS logic. A logic high selects the internal LDO for regulation of
the 5 V voltage doubler output. A logic low isolates the internal LDO from the rest of the charge
pump circuits. This allows the use of an external LDO to regulate the 5 V voltage doubler
output. The output of this LDO is then fed back into the voltage tripler and doubler/inverter
circuits of the ADM8830.
9 7
SHDN
Digital Input. 3 V CMOS logic. Active low shutdown control. This shuts down the timing
generator and enables the discharge circuit to dissipate the charge on the voltage outputs,
thus driving them to 0 V.
10 8 SCAN/
BLANK
Drive Mode Input. 3 V CMOS logic. A logic high places the part in scan (high current) mode
and the charge pump is driven by the internal oscillator. A logic low places the part in blanking
(low current) mode and the charge pump is driven by the (slower) external oscillator. This is
a power saving feature on the ADM8830.
11 9 CLKIN External CLOCK Input. During a blanking period, the oscillator circuit selects this pin to drive
the charge pump circuit. This is at a lower frequency than the internal oscillator, resulting in
lower quiescent current consumption, thus saving power.
12 10 +15VOUT +15.3 V Output Pin. This is derived by tripling the +5.1 V regulated output. A 1 μF capacitor
is required on this pin.
13, 14 11, 12 C3–, C3+ External capacitor C3 is connected between these pins. A 1 μF capacitor is recommended.
15, 16 13, 14 C2–, C2+ External capacitor C2 is connected between these pins. A 1 μF capacitor is recommended.
17, 18 15, 16 C4–, C4+ External capacitor C4 is connected between these pins. A 1 μF capacitor is recommended.
19 17 –10VOUT –10.2 V Output Pin. This is derived by doubling and inverting the +5.1 V regulated output.
A 1 μF capacitor is required on this pin.
20 18 GND Device Ground Pin.
REV. B