
PRELIMINARY TECHNICAL DATA ADMC328
–15–
REV. A
T he resultant on-times of the PWM signals shown in Figure 7
may be written as:
(
T
2
PWMCHA
PWMDT
AH
)
(
)
t
T
2
PWMTM - PWMCHA
PWMDT
t
CK
AL
CK
=
×
×
=
×
×
T he corresponding duty cycles are:
d
T
Ts
PWMCHA
PWMDT
PWMTM
d
T
Ts
PWMTM -PWMCHA
PWMDT
PWMTM
AH
AH
AL
AL
=
=
=
=
Obviously, negative values of T
and T
are not permitted
because the minimum permissible value is zero, correspond-
ing to a 0% duty cycle. In a similar fashion, the maximum
value is T
S
, corresponding to a 100% duty cycle.
T he output signals from the timing unit for operation in
double update mode are shown in Figure 8. T his illustrates a
completely general case where the switching frequency, dead
time and duty cycle are all changed in the second half of the
PWM period. Of course, the same value for any or all of these
quantities could be used in both halves of the PWM cycle.
However, it can be seen that there is no guarantee that sym-
metrical PWM signals will be produced by the timing unit in
this double update mode. Additionally, it is seen that the
dead time is inserted into the PWM signals in the same way as
in the single update mode.
PW MCHA
2
PW MSYNCW T
2
+ 1
PW MCHA
1
PW MTM
1
PW MTM
2
PW MSYNCW T
1
+ 1
AH
AL
PW MSYNC
SYSSTAT (3)
2
3
PW MDT
1
2
3
PW MDT
2
Figure 8. Typical PWM outputs of three-phase timing
unit in double update mode.
In general, the on-times of the PWM signals in double update
mode are defined by:
T
AH
= (PWMCHA
1
+ PWMCHA
2
- PWMDT
1
- PWMDT
2
)
3
t
ck
T
AL
= (PWMT M
1
+ PWMT M
2
- PWMCHA
1
- PWMCHA
2
- PWMDT
1
- PWMDT
2
)
3
t
ck
where the subscript 1 refers to the value of that register during
the first half cycle and the subscript 2 refers to the value dur-
ing the second half cycle. T he corresponding duty cycles are:
(PW M C H A1 + P W M C H A2)
(PW M T M1 + PW M T M2)
=
dA H =
TA H
TS
( PW M D T1 + PW M D T2)
(PW M T M1 + PW M T M2)
-
(PW M T M1 + PW M T M2 - PW M C H A1)
(PW M T M1 + PW M T M2)
=
dA L =
TA L
TS
(PW M T M1 + PW M T M2)
-
(PW M C H A2 + PW M D T1 + P W M D T2)
because for the completely general case in double update
mode, the switching period is given by:
T
S
= (PWMT M
1
+ PWMT M
2
)
3
T
CK
Again, the values of T
AH
and T
AL
are constrained to lie
between zero and T
S
.
PWM signals similar to those illustrated in Figure 7 and
Figure 8 can be produced on the BH, BL, CH and CL
outputs by programming the PWMCHB and PWMCHC
registers in a manner identical to that described for
PWMCHA.
T he PWM controller does not produce any PWM outputs
until all of the PWMT M, PWMCHA, PWMCHB, and
PWMCHC registers have been written to at least once.
After these registers have been written, the counters in the
three-phase timing unit are enabled. Writing to these
registers also starts the main PWM timer. If during ini-
tialization, the PWMT M register is written after the
PWMCHA, PWMCHB, and PWMCHC registers, then the
first PWMSYNC pulse (and interrupt if enabled) will be
generated (1.5
3
t
CK
3
PWMT M) seconds after the initial
write to the PWMT M register in single update mode. In
double update mode, the first PWMSYNC pulse will be
generated (t
CK
3
PWMT M) seconds after the initial write
to the PWMT M register in single update mode.
Effective PWM Resolution
In
single update mode, the same values of PWMCHA,
PWMCHB and PWMCHC are used to define the on-times
in both half cycles of the PWM period. As a result the ef-
fective resolution of the PWM generation process is 2t
(or 100 ns for a 20 MHz CLK OUT ) since incrementing
one of the duty cycle registers by 1 changes the resultant
on-time of the associated PWM signals by t
CK
in each half
period (or 2t
CK
for the full period).
In double update mode, improved resolution is possible
since different values of the duty cycles registers are used to