- 您現在的位置：買賣IC網 > PDF目錄374016 > ADMC401 (ANALOG DEVICES INC) Single-Chip, DSP-Based High Performance Motor Controller PDF資料下載
參數資料
| 型號： | ADMC401 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | Single-Chip, DSP-Based High Performance Motor Controller |
| 中文描述： | 24-BIT, 13 MHz, OTHER DSP, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數： | 30/60頁 |
| 文件大小： | 417K |
| 代理商： | ADMC401 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
REV. B
ADMC401
–30–
cycle of the signals on CH and CL. The duty cycle registers are
programmed in integer counts of the fundamental time unit,
t
CK
, and define the desired on-time of the high side PWM signal
produced by the three-phase timing unit over half the PWM pe-
riod. The switching signals produced by the three-phase timing
unit are also adjusted to incorporate the programmed dead time
value in the PWMDT register. The three-phase timing unit
produces active LO signals so that a LO level corresponds to a
command to turn on the associated power device.
A typical pair of PWM outputs (in this case for AH and AL)
from the timing unit are shown in Figure 22 for operation in
single update mode. All illustrated time values indicate the
integer value in the associated register and can be converted to
time by simply multiplying by the fundamental time increment,
t
CK
. First, it is noted that the switching patterns are symmetrical
about the midpoint of the switching period in this single up-
date mode since the same values of PWMCHA, PWMTM and
PWMDT are used to define the signals in both half cycles of the
period. It can be seen how the programmed duty cycles are
adjusted to incorporate the desired dead time into the resultant
pair of PWM signals. Clearly, the dead time is incorporated by
moving the switching instants of both PWM signals (AH and
AL) away from the instant set by the PWMCHA register. Both
switching edges are moved by an equal amount (PWMDT
×
t
CK
) to preserve the symmetrical output patterns. Also shown is
the PWMSYNC pulse whose width is set by the PWMSYNCWT
register and Bit 3 of the SYSSTAT register, which indicates
whether operation is in the first or second half cycle of the PWM
period.
PWMSYNC
AH
AL
PWMCHA
PWMCHA
2
PWMDT
PWMSYNCWT + 1
2
PWMDT
SYSSTAT (3)
PWMTM
PWMTM
Figure 22. Typical PWM Outputs of Three-Phase Timing
Unit in Single Update Mode (Active LO Waveforms)
The resultant on-times of the PWM signals over the full PWM
period (two half periods) produced by the PWM timing unit,
and illustrated in Figure 22, may be written as:
= ×
(
= ×
(
and the corresponding duty cycles are:
T
PWMCHA PWMDT
t
AH
CK
)
×
2
–
T
PWMTM
PWMCHA PWMDT
t
AL
CK
)
×
2
–
–
d
T
T
PWMCHA PWMDT
PWMTM
AH
AH
S
=
=
–
d
T
T
PWMTM
PWMCHA PWMDT
PWMTM
AL
AL
S
=
=
–
–
Obviously negative values of
T
AH
and
T
AL
are not permitted and
the minimum permissible value is zero, corresponding to a 0%
duty cycle. In a similar fashion, the maximum value is T
S
, corre-
sponding to a 100% duty cycle.
The output signals from the timing unit for operation in double
update mode are shown in Figure 23. This illustrates a com-
pletely general case where the switching frequency, dead time
and duty cycle are all changed in the second half of the PWM
period. Of course, the same value for any or all of these quanti-
ties could be used in both halves of the PWM cycle. However, it
can be seen that there is no guarantee that symmetrical PWM
signals will be produced by the timing unit in this double update
mode. Additionally, it is seen that the dead time is inserted into
the PWM signals in the same way as in the single update mode.
PWMCHA
2
2
PWMDT
1
2
PWMDT
2
PWMSYNCWT
2
+ 1
PWMCHA
1
PWMTM
1
PWMTM
2
PWMSYNCWT
1
+ 1
AH
AL
PWMSYNC
SYSSTAT (3)
Figure 23. Typical PWM Outputs of Three-Phase Timing
Unit in Double Update Mode (Active LO Waveforms)
In general the on-times of the PWM signals over the full PWM
period in double update mode can be defined as:
(
(
where the subscript 1 refers to the value of that register during
the first half cycle and the subscript 2 refers to the value during
the second half cycle. The corresponding duty cycles are:
T
PWMCHA
PWMCHA
PWMDT
PWMDT
t
AH
CK
=
+
)
×
1
2
1
2
–
–
T
PWMTM
PWMTM
PWMCHA
PWMCHA
PWMDT
PWMDT
t
AL
CK
=
+
)
×
1
2
1
2
1
2
–
–
–
–
d
T
T
PWMCHA
PWMCHA
PWMTM
PWMDT
PWMTM
PWMDT
AH
AH
S
=
=
+
+
1
2
1
2
1
2
–
–
since for the completely general case in double update mode,
the switching period is given by:
d
T
T
PWMTM
PWMTM
PWMCHA
PWMTM
PWMCHA
PWMTM
PWMDT
PWMDT
AL
AL
S
=
=
+
+
+
1
2
1
2
1
2
1
2
–
–
–
T
PWMTM
PWMTM
t
S
CK
=
+
(
)
×
1
2
Again, the values of T
AH
and T
AL
are constrained to lie between
zero and T
S.
Similar PWM signals to those illustrated in Figure
22 and Figure 23 can be produced on the BH, BL, CH and CL
outputs by programming the PWMCHB and PWMCHC registers
in a manner identical to that described for PWMCHA.
Special Consideration for PWM Operation in
Overmodulation
The PWM Timing Unit is capable of producing PWM signals
with variable duty cycle values at the PWM output pins. At the
extremities of the modulation process, both 0% and 100%
modulation are possible. These two modes are termed
full OFF
and
full ON
respectively. In between, for other duty cycle val-
ues, the operation is termed
normal modulation
.
相關PDF資料 |
PDF描述 |
|---|---|
| ADMC401-ADVEVALKIT | Circular Connector; No. of Contacts:5; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:10-5 RoHS Compliant: No |
| ADMC401-PB | Single-Chip, DSP-Based High Performance Motor Controller |
| ADMCF340 | DashDSPTM 64-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End |
| ADMCF340BST | DashDSPTM 64-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End |
| ADMCF340-EVALKIT | Circular Connector; No. of Contacts:7; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:10-99 RoHS Compliant: No |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADMC401-ADVEVALKIT | 制造商:AD 制造商全稱:Analog Devices 功能描述:Single-Chip, DSP-Based High Performance Motor Controller |
| ADMC401BST | 制造商:Analog Devices 功能描述:DSP Motor Controller 144-Pin LQFP 制造商:Analog Devices 功能描述:IC MOTOR CONTROLLER |
| ADMC401BSTZ | 功能描述:IC DSP 8CH 12BIT MOTCTRL 144LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:電機控制 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADMC401BSTZKL1 | 制造商:Analog Devices 功能描述: |
| ADMC401-PB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Single-Chip, DSP-Based High Performance Motor Controller |
發布緊急采購，3分鐘左右您將得到回復。