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參數(shù)資料
| 型號(hào)： | ADMCF341 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | DashDSP⑩ 28-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End |
| 中文描述： | DashDSP⑩28引腳閃存混合信號(hào)增強(qiáng)的DSP與模擬前端 |
| 文件頁(yè)數(shù)： | 19/36頁(yè) |
| 文件大小： | 1106K |
| 代理商： | ADMCF341 |
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REV. 0
ADMCF341
–19–
100
10
1
1 10 100
C
N
TUNED I
CONST
DEFAULT I
CONST
Figure 14. Timing Capacitor Selection
Analog Front End
The main analog inputs of the ADMCF341 (I
SENSE
1 to I
SENSE
3)
are connected to the ADC converter through three front end
blocks. Figure 15 shows the block diagram of a single analog
front end.
SHA TIMER
REGISTER
SHA
STATE
MACHINE
M
OVERCURRENT
COMPARATOR
SHA TIMER
COUNTER
VOLTAGE (THIS IS NOT AVAILABLE EXTERNALLY ON THE ADMCF341)
CURRENT
PWMSYNC
CLOCKOUT
MODECTRL REGISTER
CHANNEL SELECTION (I
SENSE
/V)
ADC CONVERSION
STATUS BIT
(ADC REGISTER)
SHA
–2.5
VxL
(TO ADC)
TRIP
(TO
PWMTRIP
FILTER)
TRIP REF HIGH
TRIP REF LOW
Figure 15. Analog Front End Block Diagram
N–1
N
N+1
N+2
N+3
N+4
N+5
1 2
3 4
5 6
7 8
9 10
11 12
CYCLE
PWMSYNC
VC
SHA TIMER
COUNTER
SHA STATUS
I
SENSE
INPUT
ADC REGISTER
X T H T H H T H
DATA READY
SAMPLED ON
CYCLE N–2
INVALID
LSB = 1
DATA READY
SAMPLED ON
CYCLE N
INVALID
LSB = 1
DATA READY
SAMPLED ON
CYCLE N+2
DATA READY
SAMPLED ON
CYCLE N+4
S
S
S
S
T
SAMPLE
T
SAMPLE
T
SAMPLE
T
SAMPLE
TRACK
Figure 16. ADC Conversion Sequence of a Current Input
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