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參數資料
| 型號： | ADMCF341BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DashDSP⑩ 28-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End |
| 中文描述： | 0-BIT, 10 MHz, OTHER DSP, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數： | 27/36頁 |
| 文件大小： | 1106K |
| 代理商： | ADMCF341BR |
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REV. 0
ADMCF341
–27–
Table XIII. DSP Core Registers
Address (hex)
Name
Bits
Function
0x3FFF
0x3FFE
0x3FFD
0x3FFC
0x3FFB
0x3FFA
0x3FF9
0x3FF8
0x3FF7
0x3FF6
0x3FF5
0x3FF4
0x3FF3
0x3FF2
0x3FF1
0x3FF0
0x3FEF
SYSCNTL
MEMWAIT
TPERIOD
TCOUNT
TSCALE
SPORT0_RX_WORDS1
SPORT0_RX_WORDS0
SPORT0_TX_WORDS1
SPORT0_TX_WORDS0
SPORT0_CTRL_REG
SPORT0_SCLKDIV
SPORT0_RFSDIV
SPORT0_AUTOBUF_CTRL
SPORT1_CTRL_REG
SPORT1_SCLKDIV
SPORT1_RFSDIV
SPORT1_AUTOBUF_CTRL
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[7 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
System Control Register
Memory Wait State Control Register
Interval Timer Period Register
Interval Timer Count Register
Interval Timer Scale Register
SPORT0 Multichannel Word 1 Receive
SPORT0 Multichannel Word 0 Receive
SPORT0 Multichannel Word 1 Transmit
SPORT0 Multichannel Word 0 Transmit
SPORT0 Control Register
SPORT0 Clock Divide Register
SPORT0 Receive Frame Sync Divide
SPORT0 Autobuffer Control Register
SPORT1 Control Register
SPORT1 Clock Divide Register
SPORT1 Receive Frame Sync Divide
SPORT1 Autobuffer Control Register
FLASH MEMORY CONTROL REGISTER
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0x2080
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
FLASH MEMORY ADDRESS REGISTER
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x2081
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
ALWAYS READ 0
ADDRESS 11 0
FLASH MEMORY DATA REGISTER LOW (FMDRL)
12
11
10
9
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
7
6
5
4
3
2
1
0
RESERVED
ALWAYS READ 0
0x2083
STATUS 5 0
DATA 7 0
FLASH MEMORY DATA REGISTER HIGH (FMDRH)
12
11
10
9
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
7
6
5
4
3
2
1
0
0x2082
DATA 23 8
MOST SIGNIFICANT BIT IS ON THE LEFT. FOR EXAMPLE, DATA23 IS BIT 15 OF FMDRH.
BOOT MEMORY FLASH CODE
Figure 22. Configuration of Flash Memory Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written as shown.
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