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參數資料
型號: ADN2811ACP-CML-RL
廠商: ANALOG DEVICES INC
元件分類: 數字傳輸電路
英文描述: OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp
中文描述: CLOCK RECOVERY CIRCUIT, QCC48
封裝: 7 X 7 MM, LEAD FREE, MO-220-VKKD-2, LFCSP-48
文件頁數: 3/16頁
文件大小: 359K
代理商: ADN2811ACP-CML-RL
REV. A
ADN2811
–3–
Parameter
Conditions
Min
Typ
Max
Unit
CML OUTPUTS (CLKOUTP/N, DATAOUTP/N)
Single-Ended Output Swing
Differential Output Swing
Output High Voltage
Output Low Voltage
Rise Time
Fall time
Setup Time
V
SE
(See Figure 3)
V
DIFF
(See Figure 3)
V
OH
V
OL
20%–80%
80%–20%
T
S
(See Figure 1)
OC-48
T
H
(See Figure 1)
OC-48
300
600
455
910
VCC
600
1200
mV
mV
V
V
ps
ps
VCC – 0.6
VCC – 0.3
150
150
84
84
140
ps
Hold Time
150
ps
REFCLK DC INPUT CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Common-Mode Level
@ REFCLKP or REFCLKN
0
100
VCC
V
mV
V
DC-Coupled, Single-Ended
VCC/2
TEST DATA DC INPUT
CHARACTERISTICS
4
(TDINP/N)
Peak-to-Peak Differential Input Voltage
CML Inputs
0.8
V
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
V
IH
V
IL
V
IN
= 0.4 V or V
IN
= 2.4 V
2.0
V
V
0.8
+5
–5
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
V
OH
, I
OH
= –2.0 mA
V
OL
, I
OL
= +2.0 mA
2.4
V
V
0.4
NOTES
1
PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity.
2
PWD measurement made on quantizer outputs in BYPASS mode.
3
Measurement is equipment limited.
4
TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.
Specifications subject to change without notice.
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相關代理商/技術參數
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