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參數資料
| 型號： | ADN8820-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | EDFA and CW Laser Controller |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC48 |
| 封裝： | 7 X 7 MM, MO-220-VKKD-2, LFCSP-48 |
| 文件頁數： | 7/9頁 |
| 文件大小： | 288K |
| 代理商： | ADN8820-REEL7 |
ADN8820
Name
DITHER GENERATOR
DSEL/SD
Preliminary Technical Data
Rev. PrB | Page 7 of 9
Pin
Function
Connections
External voltage
21
4-level logic input to set dither frequency or engage
shutdown
Sets dither current as a percentage of the laser
diode current
Optional dither AC current to laser diode
DCTL
36
Resistor (R
DCTL
) to ground
DO
35
To laser diode through 1 nF series capacitor
External logic voltage
External logic voltage
External voltage
470 pF soft-start capacitor to ground; optional external
FET can pull down to engage standby
LOGIC INPUTS
MODE1
MODE0
DSEL/SD
SS/SB
18
19
21
25
Sets control loop mode (see Table I)
Sets control loop mode (see Table I)
Pulling voltage low engages shutdown
Pulling voltage low engages standby
LOGIC OUTPUTS
CLGD
20
Logic high if EAOUT is within 5% to 95% of AVDD;
Logic low otherwise
Power for output amplifiers and digital sections
Low noise power for TIAs, limiter section, and EA
Current return for output amplifiers
Low noise ground
2.5 V reference voltage
POWER
PVDD
AVDD
PGND
AGND
VREF
29, 34
43
32
14
13
3.0 V to 5.5 V
3.0 V to 5.5 V
0 V
0 V
Can be used as refernce for VB, VBLP, SET, and limiter
inputs
TABLE 4. MODE CONTROL LOGIC
Error Amplifier
-Input
+Input
EANLP
SET
MODE Inputs
MODE1
0
Mode Setting
Constant Current
MUX
Output
LIO
Description
Maintains a fixed current through laser diode;
generally used for calibration.
Maintains a constant optical output power from
laser diode.
Maintains a constant optical power at output of
EDFA.
Monitors both input and output optical power
to maintain constant gain from optical amplifier.
MODE0
0
0
1
Constant Laser Power
EANLP
SET
LPO
1
0
Constant Ouptut Power
EANOP
SET
OPO
1
1
Constant Gain
EANOP
IPO
OPO
TABLE 5. PWM CLOCK FREQUENCY SELECTION LEVELS
DSEL/SD (V)
Min
Max
Mode
0
0.5
Shutdown
0.7
1.2
Active
1.3
1.8
Active
2.0
VDD
Active
PWM Clock Frequency
Division
N/A
f
DITHER
÷
2
f
DITHER
÷
4
f
DITHER
÷
8
Note: f
DITHER
is the ADN8820 dither frequency and is set by a resistor connected from RT to ground.
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