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參數(shù)資料
| 型號(hào)： | ADN8820 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 模擬信號(hào)調(diào)理 |
| 英文描述： | EDFA and CW Laser Controller |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC48 |
| 封裝： | 7 X 7 MM, MO-220-VKKD-2, LFCSP-48 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大小： | 288K |
| 代理商： | ADN8820 |
ADN8820
PIN FUNCTIONS
Name
AMPLIFIER INPUTS
IPDIN
LPDIN
OPDIN
VB
VBLP
CSP
CSN
LIMIT INPUTS
VLIM
ILIM
OPLIM
LPLIM
IPMIN
ERROR (COMPENSATION) AMPLIFIER (EA)
EANLP
41
Preliminary Technical Data
Rev. PrB | Page 6 of 9
Pin
Function
Connections
EDFA input photodiode and feedback resistor
Laser photodiode and feedback resistor
EDFA output photodiode and feedback resistor
External bias voltage required
External bias voltage required
High-side of laser current sense resistor (50 m
typ.)
Low-side of laser current sense resistor (50 m
typ.)
External voltage required
External voltage or no connection (defaults to 2.5 V)
External voltage or no connection (defaults to 2.5 V)
External voltage or no connection (defaults to 2.5 V)
External voltage required
Internally connects inverting input of EA to laser diode
compensation network
Internally connects inverting input of EA to EDFA
compensation network
Internal connection to linear output amplifier
Connects to two external compensation networks: one
for EDFA loop, one for laser diode loop
R-C network to ground
External voltage or DAC
3
6
9
2
5
37
38
1
45
47
46
48
Input to TIA for EDFA input photodiode
Input to TIA for laser photodiode
Input to TIA for EDFA output photodiode
Bias voltage for EDFA input and output photodiodes
Bias voltage for laser photodiode
Non-inverting input of current sense amplifier
Inverting input of current sense amplifier
Laser diode voltage will not exceed VLIM
Limits output voltage if LIO > ILIM
Limits output voltage if OPO > OPLIM
Limits output voltage if LPO > LPLIM
Limits output voltage if IPO is lower than IPMIN
Compensation network for laser diode loop
EANOP
40
Compensation network for EDFA loop
EAOUT
MUX
39
42
Output of compensation amplifier
Allows separate compensation for EDFA and laser
diode
Compensation for limiter section
Sets output power or current based on MODE
settings
OPCMP
SET
44
8
POWER OUTPUT AMPLIFIERS
LINOUT
PGATE
NGATE
SWITCH
FB
PWMCMP1
PWMCMP2
SS/SB
Laser diode through 1
series resistor
Gate of external PMOS for PWM output
Gate of external NMOS for PWM output
Drains of external NMOS, PMOS, and input of L-C filter
Output of L-C filter and laser diode
Series R-C networks to FB and PWMCMP2
Series R-C to PWMCMP1
Optional external FET can pull down and to engage
standby mode
Feedback resistor to IPDIN
Feedback resistor to OPDIN
Feedback resistor to LPDIN
To SET pin of additional ADN8820 device in multi-
pump optical amplifier applications
Internal connection to linear output amplifier
Ground or external clock
Optional connection to SYNCIN of additional ADN8820
device
R-C network to ground
External voltage or no connection (default is 0.7V)
Resistor (R
T
) to ground
33
30
31
28
24
23
22
25
Linear amplifier output
PWM switching for PMOS
PWM switching for NMOS
PWM amplifier output
Feedback input for PWM amplifier
Compensation for PWM amplifier
Compensation for PWM amplifier
Constant current charges external capacitor to soft-
start PWM output from 0% duty cycle
OUTPUT MONITOR VOLTAGES
IPO
OPO
LPO
LIO
DUAL
4
10
7
11
12
Output of EDFA input photodiode TIA
Output of EDFA output photodiode TIA
Output of laser diode photodiode TIA
Output of current sense amplifier
Compares LIO to 90% of ILIM
EAOUT
OSCILLATOR SECTION
SYNCIN
SYNCOUT
39
Output of compesnation amplifier
27
26
Optional clock input signal for PLL
Follows rising edge of SYNCIN plus phase shift
CMPOSC
PHASE
RT
16
17
15
Compensation for synchronizing PLL
Sets rising edge phase shift of SYNCOUT
Sets PWM clock frequency
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