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參數(shù)資料
| 型號(hào)： | ADP3170 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Charger front end protection IC with 30V max Vin and 4.5V LDO output 8-WSON 0 to 125 |
| 中文描述： | VRM電源單相兼容8.5核心控制器 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 183K |
| 代理商： | ADP3170 |
REV. 0
ADP3170
–11–
R
R
R
R
R
k
M
k
k
A
T
OGM
B
A
=
=
=
1
1
1
1
1
1
1
8 88
.
1
1
29 7
12 83
.
–
–
–
–
.
(13)
Choosing the nearest 1% resistor value gives
R
A
=
12.7
k
.
C
OUT
Selection
The required equivalent series resistance (ESR) and capacitance
drive the selection of the type and quantity of the output capaci-
tors. The ESR of the output filter capacitor bank must be equal
to or less than the specified output resistance of the voltage
regulator (3.2 m
). The capacitance must be large enough that
the voltage across the capacitor, which is the sum of the resistive
and capacitive voltage drops, does not move below or above the
initial resistive step while the inductor current ramps up or
down to the value corresponding to the new load current. One
can use, for example, eight ZA series capacitors from Rubycon,
which have a maximum ESR of 24 m
. These eight 1000
μ
F
capacitors would give an ESR of 3 m
.
As long as the capacitance of the output capacitor is above a
critical value, and the regulating loop is compensated with
Analog Devices’ proprietary compensation technique (ADOPT),
the actual value has no influence on the peak-to-peak deviation
of the output voltage to a full step change in the load current.
The critical capacitance can be calculated as follows:
I
R
V
V
A
m
V
.
1 8
×
+
3 2
The equivalent capacitance of the eight ZA series Rubycon
capacitors is 8
×
1 mF = 8 mF. In this case, the total capacitance
is safely above the critical value.
Feedback Loop Compensation Design for ADOPT
Optimized compensation of the ADP3170 allows the best pos-
sible containment of the peak-to-peak output voltage deviation.
The output current slew rate of any practical switching power
converter is inherently limited by the inductor to a value much
less than the slew rate of the load. Therefore, any sudden change
of load current will initially flow through the output capacitors,
and assuming that the capacitance of the output capacitor is
larger than the critical value defined by Equation 14, this will
produce a peak output voltage deviation equal to the ESR of the
output capacitor times the load current change.
The optimal implementation of voltage positioning, ADOPT,
will create an output impedance of the power converter that is
entirely resistive over the widest possible frequency range,
including dc, and equal to the specified dc output resistance.
With the wide-band resistive output impedance the output
voltage will droop in proportion with the load current at any
load current slew rate; this ensures the optimal positioning
and allows the minimization of the output capacitor.
With an ideal current-mode controlled converter, where the
inductor current would respond without delay to the command
signal, the resistive output impedance could be achieved by
having a single-pole roll-off of the voltage gain of the voltage-
error amplifier. The pole frequency must coincide with the ESR
zero of the output capacitor.
The ADP3170 uses peak-current control, which is known to
have a nonideal, frequency-dependent command signal-to-
inductor current transfer function. The frequency dependence
manifests in the form of a pair of complex conjugate poles at
one-half of the switching frequency. A purely resistive output
impedance could be achieved by canceling the complex conju-
gate with zeros at the same complex frequencies and adding a
third pole equal to the ESR zero of the output capacitor. Such a
compensating network would be quite complicated. Fortu-
nately, in practice, it is sufficient to cancel the pair of complex
conjugate poles with a single real zero placed at one-half of the
switching frequency.
Although the end result is not a perfectly resistive output imped-
ance, the remaining frequency dependence causes only a slight
percentage of deviation from the ideal resistive response. The
single-pole and single-zero compensation can be easily imple-
mented by terminating the g
m
error amplifier with the parallel
combination of a resistor (R
T
) and a series RC network. The
value of the terminating resistor R
T
was determined previously;
the capacitance and resistance of the series RC network are
calculated as follows:
C
C
ESR
R
C
mF
8 88
.
m
k
nF
OC
OUT
T
OC
=
×
=
×
=
8
3
2 7
.
(15)
The closest standard value is 2.7
nF
. The series resistance is:
R
C
f
R
nF
kHz
Z
OC
MIN
Z
=
×
×
=
×
×
=
2
π
2
2 7
.
188
1255
π
(16)
The nearest standard 5% resistor value is 1.2 k
. Note that this
resistor is only required when C
OUT
approaches C
CRIT
(within
25% or less). In this example, C
OUT
>> C
CRIT
, and R
Z
can
therefore be omitted.
C
L
C
mV
H
mF
OUT CRIT
(
O
OUT
OUT
OUT CRIT
(
)
)
(
–)
[–
])
.
=
×
+
×
=
×
=
23
29
1
4 06
μ
(14)
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