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參數(shù)資料
| 型號： | ADP3171 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Charger front end protection IC with 30V max Vin and 4.5V LDO output 8-WSON 0 to 125 |
| 中文描述： | 同步降壓控制器，配有雙線性穩(wěn)壓器控制器 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 310K |
| 代理商： | ADP3171 |
REV. 0
ADP3171
–9–
Power MOSFETs
Two external N-channel power MOSFETs must be selected for
use with the ADP3171, one for the main switch and one for the
synchronous switch. The main selection parameters for the power
MOSFETs are the threshold voltage (V
GS(TH)
), the ON resistance
(R
DS(ON)
), and the gate charge (Q
G
). Logic level
MOSFETs are
highly recommended. Only logic level MOSFETs with V
GS
ratings
higher than the absolute maximum value of V
CC
should be used.
The maximum output current I
O(MAX)
determines the R
DS(ON)
requirement for the two power MOSFETs. When the ADP3171
is operating in continuous mode, the simplifying assumption
can be made that one of the two MOSFETs is always conduct-
ing the average load current. For V
IN
= 5 V and V
OUT
= 1.5 V,
the maximum duty ratio of the high-side FET is:
(
=
×
(
1
192
3 5
D
f
t
D
kHz
s
HSF MAX
(
MIN
OFF
HSF MAX
(
)
)
–
–
.
%
=
+
)
)
=
1
33
μ
(20)
The maximum duty ratio of the low-side (synchronous rectifier)
MOSFET is:
D
D
LSF MAX
(
HSF MAX
(
)
)
–
%
=
=
1
67
(21)
The maximum rms current of the high-side MOSFET is:
I
D
I
I
I
I
I
A
A
A
A
A
HSF MAX
(
HSF MAX
(
L VALLEY
(
L VALLEY
(
L PEAK
(
L PEAK
(
HSF MAX
(
)
)
)
)
)
)
)
(
)
.
.
( .
3 75
.
)
.
.
=
×
+
×
+
=
×
+
×
3
+
=
2
2
2
2
3
0 33
3 75
6 25
6 25
2 9
(22)
The maximum rms current of the low-side MOSFET is:
I
D
I
I
I
I
I
A
A
A
A
A
LSF MAX
(
LSF MAX
(
L VALLEY
(
L VALLEY
(
L PEAK
(
L PEAK
(
LSF MAX
(
)
)
)
)
3
)
)
)
(
)
)
.
.
( .
(
.
)
.
.
=
×
+
×
+
=
×
+
×
3
+
)
=
2
2
2
2
0 67
3 75
3 75
6 25
6 25
4 1
(23)
The R
DS(ON)
for each MOSFET can be derived from the allowable
dissipation. If 10% of the maximum output power is allowed for
MOSFET dissipation, the total dissipation will be:
P
P
V
I
6 5
V
A
mW
D FETs
(
OUT
.
OUT MAX
(
.
D FETs
(
)
)
)
.
.
=
=
×
×
×
=
0 1
0 1 1 5
975
(24)
Allocating half of the total dissipation for the high-side MOSFET
and half for the low-side MOSFET, and assuming that the resistive
loss of the high-side MOSFET is one-third and the switching
loss is two-thirds of its total, the required maximum MOSFET
resistances will be:
R
P
I
mW
.
2 9
A
m
DS ON HSF
(
D FETs
(
HSF MAX
(
)
)
)
=
×
=
×
=
3
975
3
38
2
2
(25)
R
P
I
mW
.
4 1
A
m
DS ON LSF
(
D FETs
(
LSF MAX
(
)
)
)
=
×
=
×
=
2
975
2
29
2
2
(26)
Note that there is a trade-off between converter efficiency and cost.
Larger MOSFETs reduce the conduction losses and allow higher
efficiency, but increase the system cost. A Fairchild FDB6982
dual MOSFET (high-side R
DS(ON)
= 28 m
nominal, 35 m
worst-case; and low-side R
DS(ON)
= 16 m
nominal, 22 m
worst-case) is a good choice in this application.
With this choice, the high-side MOSFET dissipation is:
P
R
I
V
I
Q
f
I
V
Q
f
P
m
A
A
nC
A
1
kHz
V
nC
kHz
mW
HSF
DS ON HSF
(
HSF MAX
(
IN
L PEAK
(
G
MIN
G
IN
RR
MIN
HSF
=
×
+
×
×
×
×
+
×
×
=
×
+
+
×
2
×
×
+
×
×
=
)
)
)
.
.
2
2
2
35
2 9
5
6 25
12
192
5
19
192
349
(27)
where the second term represents the turn-off loss of the MOSFET
and the third term represents the turn-on loss due to the stored
charge in the body diode of the low-side MOSFET. In the sec-
ond term,
Q
G
is the gate charge to be removed from the gate for
turn-off and
I
G
is the gate turn-off current. From the data sheet,
the value of
Q
G
for the FDS6982 is 12 nC and the peak gate
drive current provided by the ADP3171 is about 1 A. In the
third term,
Q
RR
is the charge stored in the body diode of the
low-side MOSFET at the valley of the inductor current. The
data sheet of the FDS6982 shows a value of 19 nC for this
parameter.
The low-side MOSFET dissipation is:
P
R
I
P
m
A
mW
LSF
DS ON LSF
(
22
LSF MAX
=
LSF
=
=
×
×
)
(
)
.
2
2
4 1
370
(28)
Note that there are no switching losses in the low-side MOSFET.
C
IN
Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of the
high-side MOSFET is a square wave with a duty ratio of V
OUT
/
V
lN
and an amplitude of one-half of the maximum output current.
To
prevent large voltage transients, a low ESR input capacitor
sized
for the maximum rms current must be used. The maximum
rms
capacitor current is given by:
I
I
D
D
I
A
A
C RMS
(
O
HSF
HSF
C RMS
(
)
)
–
.
–0 33
.
=
×
=
×
=
2
2
5
0 33
2 4
(29)
For a ZA-type capacitor with 1000
μ
F capacitance and 6.3 V
voltage rating, the ESR is 24 m
and the maximum allowable
ripple current at 100 kHz is 2 A. At 105
°
C, at least two such
capacitors should be connected in parallel to handle the calcu-
lated ripple current. At 50
°
C ambient, however, a higher ripple
current can be tolerated, so one capacitor is adequate.
The ripple voltage across the input capacitor is:
V
I
ESR
n
D
×
n
C
f
V
I
m
1
mF
kHz
mV
C RIPPLE
(
O
C
C
HSF MAX
(
C
IN
MIN
C RIPPLE
(
O
)
)
)
.
×
=
×
+
×
=
×
+
=
24
0 33
1 1
192
26
(30)
Linear Regulators
The linear regulators provide a low-cost, convenient, and versatile
solution for generating moderate current supply rails. The maxi-
mum output load current is determined by the size and thermal
impedance of the external N-channel power MOSFET that is
placed in series with the supply and controlled by the ADP3171.
The output voltage is sensed at the LRFB
×
pin and compared
to an internal reference voltage in a negative feedback loop that
keeps the output voltage in regulation. If the load is reduced or
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