
REV. PrD
–2–
PRELIMINARY TECHNICAL DATA
ADP3203–SPECIFICATIONS
1
DSHIFT are open, BOM = H, DSLP = H, DPRSLP = L, unless otherwise noted) Current sunk by a pin has a positive sign, sourced by a pin has a
negative sign. Negative sign is disregarded for min and max values.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
SUPPLY-UVLO-SHUTDOWN
Normal Supply Current
UVLO Supply Current
Shutdown Supply Current
I
CC
I
CCUVLO
I
CCSD
7
15
425
mA
μ
A
μ
A
SD
= L, 3.0 V
≤
VCC
≤
3.6 V
10
UVLO Threshold
SD
= H
V
CC
ramping up, V
SS
= 0 V
V
CC
ramping down,
V
SS
floating
V
CCH
V
CCL
2.9
V
V
2.65
UVLO Hysteresis
V
CCHYS
50
mV
Shutdown Threshold (CMOS Input)
V
SDTH
V
CC
/2
V
POWERGOOD-CORE FEEDBACK
Core Feedback Threshold Voltage
V
COREFBH
0.9 V < V
< 1.675 V
V
COREFB
ramping up
V
COREFB
ramping down
V
COREFB
ramping up
V
COREFB
ramping down
1.12 V
DAC
1.10
V
DAC
0.88
V
DAC
0.86
V
DAC
1.14
V
DAC
V
1.12
V
DAC
V
0.90
V
DAC
V
0.88
V
DAC
V
Power Good Output Voltage
(open drain output)
V
PWRGD
V
COREFB
= V
V
COREFB
= 0.8 V
DACOUT
0.95
V
CC
0
V
CC
0.8
V
V
Masking Time
2
t
PWRGD,MSK
6
V
CC
=
3.3 V
100
μ
s
SOFT-START/HICCUP TIMER
Charge/Discharge Current
I
SS
V
SS
= 0 V
V
SS
= 0.5 V
V
REG
= 1.25 V,
V
RAMP
= V
COREFB
= 1.27 V
V
SS
ramping down
V
SS
ramping up
V
RAMP
= V
COREFB
= 1.27 V
V
SS
ramping up
–
16
0.5
μ
A
μ
A
Soft-Start Enable/Hiccup
Termination Threshold
V
SSENDWN
V
SSENUP
V
SSTERM
80
150
200
mV
mV
7
Soft-Start Termination/Hiccup
Enable Threshold
1.75
2.00
2.25
V
VID DAC
VID Input Threshold (CMOS Inputs)
VID Input Current
(Internal Active Pull-up)
Output Voltage
Accuracy
V
VID0..4
I
VID0..4
V
CC
/2
90
V
μ
A
VID 0..4 = L
V
DAC
V
DAC
/V
DAC
See VID Code Table 1
0.850 V < V
DAC
< 1.750 V
0.600 V < V
< 0.825 V
V
DAC
= 0.5 V, C
DAC
= 10 nF
0.600
–1.0
–8.5
1.750
+1.0
+8.5
V
%
mV
μ
s
Settling Time
2
t
DACS
3
3.5
Notes:
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Guaranteed by characterization.
3
Measured from 50% of VID code transition amplitude to the point where V
DACOUT
settles within ±1% of its steady state value.
4
40 mV
PP
amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.
5
Measured between the 30% and 70% points of the output voltage swing.
6
Two test conditions: 1)PWRGD is OK but forced to fail by applying an out-of-the-CoreGood-window voltage (V
COREFB,BAD
= 1.0 V at V
VID
= 1.25 V setting) to
the COREFB pin right after the moment that
BOM
or DPRSLP is asserted/de-asserted. PWRGD should not fail immediately only with the specified blanking
delay time. 2) PWRGD is forced to fail (V
COREFB,BAD
= 1.0 V at V
VID
= 1.25 V setting) but gets into the CoreGood-window
(V
COREFB,GOOD
= 1.25 V) right after the moment that
BOM
or DPRSLP is asserted/de-asserted. PWRGD should not go high immediately only with the specified
blanking delay time.
7
Guaranteed by design.
( T
A
=
25 °C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, V
COREFB
=
V
DAC
(
≡
V
DACOUT
), V
REG
= V
CS–
= V
VID
= 1.25 V, R
OUT
= 100 k
, C
OUT
= 10 pF,
C
SS
= 47 nF, R
PWRGD
= 680
to 1.2 V, R
CLAMP
= 5.1 k
to VCC, HYSSET, BSHIFT,