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參數資料
| 型號： | ADP3414 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.35V) 8-SM8 -40 to 110 |
| 中文描述： | 雙舉MOSFET驅動電路 |
| 文件頁數： | 2/8頁 |
| 文件大小： | 141K |
| 代理商： | ADP3414 |
REV. 0
–2–
ADP3414–SPECIFICATIONS
1
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SUPPLY
Supply Voltage Range
Quiescent Current
VCC
ICC
Q
4.15
7.5
2
V
mA
1
PWM INPUT
Input Voltage High
2
Input Voltage Low
2
2.3
V
V
0.8
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
V
BST
–
V
SW
= 5 V
V
BST
–
V
SW
= 7 V
V
BST
–
V
SW
= 5 V
V
BST
–
V
SW
= 7 V
V
BST
–
V
SW
= 7 V, C
LOAD
= 3 nF
V
BST
–
V
SW
= 7 V, C
LOAD
= 3 nF
V
BST
–
V
SW
= 7 V
V
BST
–
V
SW
= 7 V
3.0
2.0
1.25
1.0
36
20
65
21
5.0
3.5
2.5
2.5
47
30
86
32
ns
ns
ns
ns
Output Resistance, Sinking Current
Transition Times
3
(See Figure 2)
tr
DRVH
tf
DRVH
tpdh
DRVH
tpdl
DRVH
Propagation Delay
3, 4
(See Figure 2)
LOW-SIDE DRIVER
Output Resistance, Sourcing Current
VCC = 5 V
VCC = 7 V
VCC = 5 V
VCC = 7 V
VCC = 7 V, C
LOAD
= 3 nF
VCC = 7 V, C
LOAD
= 3 nF
VCC = 7 V
VCC = 7 V
3.0
2.0
1.5
1.0
27
19
30
15
5.0
3.5
3.0
2.5
35
26
35
25
ns
ns
ns
ns
Output Resistance, Sinking Current
Transition Times
3
(See Figure 2)
tr
DRVL
tf
DRVL
tpdh
DRVL
tpdl
DRVL
Propagation Delay
3, 4
(See Figure 2)
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Logic inputs meet typical CMOS I/O conditions for source/sink current (~1
μ
A).
3
AC specifications are guaranteed by characterization, but not production tested.
4
For propagation delays,
“
tpdh
”
refers to the specified signal going high;
“
tpdl
”
refers to it going low.
Specifications subject to change without notice.
(T
A
= 0 C to 70 C, VCC = 7 V, BST = 4 V to 26 V, unless otherwise noted.)
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