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參數(shù)資料
| 型號： | ADP3417 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.35V) 8-SM8 -40 to 110 |
| 中文描述： | 雙舉MOSFET驅(qū)動電路 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 1487K |
| 代理商： | ADP3417 |
REV. A
–2–
ADP3417–SPECIFICATIONS
1
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SUPPLY
Supply Voltage Range
Quiescent Current
VCC
ISYS
4.15
13.2
7
V
mA
VCC = BST = 12 V, IN = 0 V
5
PWM INPUT
Input Voltage High
2
Input Voltage Low
2
2.5
V
V
0.8
HIGH SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times
3
V
BST
–
V
SW
= 12 V
V
BST
–
V
SW
= 12 V
See Figure 2, V
BST
–
V
SW
= 12 V,
C
LOAD
= 3 nF
See Figure 2, V
BST
–
V
SW
= 12 V,
C
LOAD
= 3 nF
See Figure 2, V
BST
–
V
SW
= 12 V,
V
BST
–
V
SW
= 12 V
1.75
1.0
45
3.0
2.5
55
ns
tr
DRVH
Transition Times
3
tf
DRVH
20
30
ns
Propagation Delay
3, 4
tpdh
DRVH
tpdl
DRVH
45
15
65
35
ns
ns
LOW SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times
3
VCC = 12 V
VCC = 12 V
See Figure 2, VCC = 12 V,
C
LOAD
= 3 nF
See Figure 2, VCC = 12 V,
C
LOAD
= 3 nF
See Figure 2, VCC = 12 V
See Figure 2, VCC = 12 V
1.75
1.0
25
3.0
2.5
35
ns
tr
DRVL
tf
DRVL
21
30
ns
Propagation Delay
3, 4
(See Figure 2)
tpdh
DRVL
tpdl
DRVL
30
10
60
20
ns
ns
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Logic inputs meet typical CMOS I/O conditions for source/sink current (~1
μ
A).
3
AC specifications are guaranteed by characterization but not production tested.
4
For propagation delays,
“
TPDH
”
refers to the specified signal going high;
“
TPDL
”
refers to it going low.
Specifications subject to change without notice.
(VCC = 12 V, BST = 4 V to 26 V, T
A
= 0 C to 70 C, unless otherwise noted.)
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