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參數資料
| 型號： | ADP5022ACBZ-6-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 17/28頁 |
| 文件大小： | 1071K |
| 描述： | IC REG TRPL BCK/LINEAR 16WLCSP |
| 產品變化通告： | 8mm Carrier Tape Changes 28/Feb/2012 |
| 標準包裝： | 1 |
| 拓撲： | 降壓（降壓）同步（2），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數： | 3 |
| 頻率 - 開關： | 3MHz |
| 電壓/電流 - 輸出 1： | 1V，600mA |
| 電壓/電流 - 輸出 2： | 1.8V，600mA |
| 電壓/電流 - 輸出 3： | 2.5V，150mA |
| 帶 LED 驅動器： | 無 |
| 帶監控器： | 無 |
| 帶序列發生器： | 是 |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFBGA，WLCSP |
| 供應商設備封裝： | 16-WLCSP |
| 包裝： | 標準包裝 |
| 其它名稱： | ADP5022ACBZ-6-R7DKR |
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ADP5022
Rev. C | Page 17 of 28
Thermal Protection
In the event that the junction temperature rises above 150癈,
the thermal shutdown circuit turns off the converters and the
LDO. Extreme junction temperatures can be the result of high
current operation, poor circuit board design, or high ambient
temperature. A 20癈 hysteresis is included so that when thermal
shutdown occurs, the bucks and LDO do not return to opera-
tion until the on-chip temperature drops below 130癈. When
coming out of thermal shutdown, soft start is initiated.
Undervoltage Lockout
To protect against battery discharge, undervoltage lockout
(UVLO) circuitry is integrated in the system. If the input
voltage on VDDA drops below a typical 2.15 V UVLO
threshold, all channels shut down. In the buck channels,
both the power switch and the synchronous rectifier turn
off. When the voltage on VDDA rises above the UVLO
threshold, the part is enabled once more.
Alternatively, the user can select device models with a UVLO
set at a higher level, suitable for USB applications. For these
models, the device hits the turn-off threshold when the input
supply drops to 3.65 V typical.
Enable/Shutdown
When all three enable pins are held low, the device is in
shutdown mode, and the input current remains below 2 糀.
BUCK SECTION
The two bucks use a fixed frequency and high speed current
mode architecture.
The bucks operate with an input voltage of 2.4 V to 5.5 V.
Control Scheme
The bucks operate with a fixed frequency, current mode PWM
control architecture at medium to high loads for high efficiency
but shift to a power save mode (PSM) control scheme at light
loads to lower the regulation power losses. When operating in
fixed frequency PWM mode, the duty cycle of the integrated
switches is adjusted and regulates the output voltage. When
operating in PSM at light loads, the output voltage is controlled
in a hysteretic manner, with higher output voltage ripple. During
part of this time, the converter is able to stop switching and
enters an idle mode, which improves conversion efficiency.
PWM Mode
In PWM mode, the bucks operate at a fixed frequency of 3 MHz
set by an internal oscillator. At the start of each oscillator cycle,
the PFET switch is turned on, sending a positive voltage across
the inductor. Current in the inductor increases until the current
sense signal crosses the peak inductor current threshold that
turns off the PFET switch and turns on the NFET synchronous
rectifier. This sends a negative voltage across the inductor,
causing the inductor current to decrease. The synchronous
rectifier stays on for the rest of the cycle. The buck regulates the
output voltage by adjusting the peak inductor current threshold.
Power Save Mode (PSM)
The bucks smoothly transition to PSM operation when the
load current decreases below the PSM current threshold. When
either of the bucks enter power save mode, an offset is induced
in the PWM regulation level, which makes the output voltage
rise. When the output voltage reaches a level approximately
1.5% above the PWM regulation level, PWM operation is
turned off. At this point, both power switches are off, and the
buck enters an idle mode. The output capacitor discharges until
the output voltage falls to the PWM regulation voltage, at which
point the device drives the inductor to make the output voltage
rise again to the upper threshold. This process is repeated while
the load current is below the PSM current threshold.
PSM Current Threshold
The PSM current threshold is set to 100 mA. The bucks employ
a scheme that enables this current to remain accurately con-
trolled, independent of input and output voltage levels. This
scheme also ensures that there is very little hysteresis between
the PSM current threshold for entry to and exit from the PSM.
The PSM current threshold is optimized for excellent efficiency
over all load currents.
Oscillator/Phasing of Inductor Switching
The ADP5022 ensures that both bucks operate at the same
switching frequency when both bucks are in PWM mode.
Additionally, the ADP5022 ensures that when both bucks are
in PWM mode, they operate out-of-phase, whereby the Buck2
PFET starts conducting exactly half a clock period after the
Buck1 PFET starts conducting.
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| ADP5023 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 3 MHz, 800 mA Buck |
| ADP5023ACPZ-1-R7 | 功能描述:IC REG TRPL BCK/LINEAR 24LFCSP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩壓器 - 線性 + 切換式 系列:- 標準包裝:2,500 系列:- 拓撲:降壓（降壓）同步（3），線性（LDO）（2） 功能:任何功能 輸出數:5 頻率 - 開關:300kHz 電壓/電流 - 輸出 1:控制器 電壓/電流 - 輸出 2:控制器 電壓/電流 - 輸出 3:控制器 帶 LED 驅動器:無 帶監控器:無 帶序列發生器:是 電源電壓:5.6 V ~ 24 V 工作溫度:-40°C ~ 85°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| ADP5023ACPZ-2-R7 | 功能描述:直流/直流開關調節器 ADJ Outputs, UVLO High RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數量: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| ADP5023ACPZ-R2 | 功能描述:直流/直流開關調節器 ADJ Outputs UVLO Low RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數量: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| ADP5023ACPZ-R7 | 功能描述:IC REG TRPL BCK/LINEAR 24LFCSP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩壓器 - 線性 + 切換式 系列:- 標準包裝:2,500 系列:- 拓撲:降壓（降壓）同步（3），線性（LDO）（2） 功能:任何功能 輸出數:5 頻率 - 開關:300kHz 電壓/電流 - 輸出 1:控制器 電壓/電流 - 輸出 2:控制器 電壓/電流 - 輸出 3:控制器 帶 LED 驅動器:無 帶監控器:無 帶序列發生器:是 電源電壓:5.6 V ~ 24 V 工作溫度:-40°C ~ 85°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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