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參數(shù)資料
| 型號(hào)： | ADS7616A4A-55 |
| 廠商： | ADATA Technology Co., Ltd. |
| 英文描述： | Synchronous DRAM(2M X 16 Bit X 4 Banks) |
| 中文描述： | 同步DRAM（2米× 16位× 4個(gè)銀行） |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大小： | 565K |
| 代理商： | ADS7616A4A-55 |
A-Data
ADS7616A4A
Synchronous DRAM
Rev 1.0 April, 2001
1
2M x 16 Bit x 4 Banks
General Description
The ADS7616A4A are four-bank Synchronous
DRAMs organized as 2,097152 words x 16 bits x 4
banks.
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
Ordering Information.
Part No.
Frequency
Interface
Package
ADS7616A4A-55
183Mhz
LVTTL
400mil 54pin TSOPII
ADS7616A4A-6
166Mhz
LVTTL
400mil 54pin TSOPII
ADS7616A4A-7
143Mhz
LVTTL
400mil 54pin TSOPII
Pin Assignment
54
53
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
52
51
50
49
48
47
46
45
44
43
36
37
35
34
33
41
42
40
39
38
32
31
30
29
Vss
DQ15
Vss
Q
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
/WE
/CAS
/RAS
/CS
BS0
BS1
A10/AP
A0
A1
A2
A3
V
DD
54-pin plastic TSOP II 400 mil
Features
JEDEC standard LVTTL 3.3V power supply
MRS Cycle with address key programs
-CAS Latency (2 & 3)
-Burst Length (1,2,4,8,& full page)
-Burst Type (sequential & Interleave)
4 banks operation
All inputs are sampled at the positive edge of
the system clock
Burst Read single write operation
Auto & Self refresh
4096 refresh cycle
DQM for masking
Package:54-pins 400 mil TSOP-Type II
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