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參數資料
型號: ADSP-21061LAS-160
廠商: ANALOG DEVICES INC
元件分類: 數字信號處理
英文描述: ADSP-2106x SHARC DSP Microcomputer Family
中文描述: 48-BIT, 40 MHz, OTHER DSP, PQFP240
封裝: METRIC, QFP-240
文件頁數: 39/47頁
文件大小: 367K
代理商: ADSP-21061LAS-160
ADSP-21061/ADSP-21061L
–39–
REV. B
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation given above. Choose
V
to be the difference between the ADSP-2106x’s output voltage
and the input threshold for the device requiring the hold time. A
typical
V will be 0.4 V. C
L
is the total bus capacitance (per
data line), and I
L
is the total leakage or three-state current (per
data line). The hold time will be t
DECAY
plus the minimum
disable time (i.e., t
DATRWH
for the write cycle).
REFERENCE
SIGNAL
t
DIS
OUTPUT STARTS
DRIVING
V
OH (MEASURED)
V
V
OL (MEASURED)
+ V
t
DECAY
t
MEASURED
V
OH (MEASURED)
V
OL (MEASURED)
2.0V
1.0V
V
OH (MEASURED)
V
OL (MEASURED)
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
t
ENA
OUTPUT
Figure 24. Output Enable/Disable
+1.5V
50pF
TO
OUTPUT
PIN
I
OL
I
OH
Figure 25. Equivalent Device Loading for AC Measure-
ments (Includes All Fixtures)
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 25). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figures 28–29,
32–33 show how output rise time varies with capacitance. Fig-
ures 30, 34 show graphically how output delays and holds vary
with load capacitance. (Note that this graph or derating does
not apply to output disable delays; see the previous section
Output Disable Time
under Test Conditions.) The graphs of
Figures 28, 29 and 30 may not be linear outside the ranges
shown.
INPUT OR
OUTPUT
1.5V
1.5V
Figure 26. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
相關PDF資料
PDF描述
ADSP-21061LAS-176 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061KS-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061KS-200 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061LKB-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061LKB-176 ADSP-2106x SHARC DSP Microcomputer Family
相關代理商/技術參數
參數描述
ADSP-21061LAS-176 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 44MHz 44MIPS 240-Pin MQFP Tray 制造商:Analog Devices 功能描述:IC MICROCOMPUTER DSP
ADSP-21061LASZ-176 功能描述:IC DSP CONTROLLER 32BIT 240MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP(數字式信號處理器) 系列:SHARC® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C,McASP,McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA,FCBGA 供應商設備封裝:548-FCBGA(27x27) 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
ADSP-21061LKB-160 功能描述:IC DSP CONTROLLER 32BIT 225BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP(數字式信號處理器) 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI,以太網,RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA,FCBGA 供應商設備封裝:431-FCPBGA(20x20) 包裝:托盤
ADSP-21061LKB-176 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer Family
ADSP-21061LKBZ-160 功能描述:IC DSP CONTROLLER 32BIT 225-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP(數字式信號處理器) 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI,以太網,RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA,FCBGA 供應商設備封裝:431-FCPBGA(20x20) 包裝:托盤
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