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參數資料
| 型號： | ADSP-21160NCB-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | 64-BIT, 50 MHz, OTHER DSP, PBGA400 |
| 封裝： | 27 X 27 MM, METRIC, PLASTIC, MS-034BAL-2, BGA-400 |
| 文件頁數： | 1/60頁 |
| 文件大小： | 1296K |
| 代理商： | ADSP-21160NCB-100 |
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SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SHARC
Digital Signal Processor
ADSP-21160M/ADSP-21160N
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2010 Analog Devices, Inc. All rights reserved.
SUMMARY
High performance 32-bit DSP—applications in audio, medi-
cal, military, graphics, imaging, and communication
Super Harvard architecture—4 independent buses for dual
data fetch, instruction fetch, and nonintrusive, zero-over-
head I/O
Backward compatible—assembly source level compatible
with code for ADSP-2106x DSPs
Single-instruction, multiple-data (SIMD) computational
architecture—two 32-bit IEEE floating-point computation
units, each with a multiplier, ALU, shifter, and register file
Integrated peripherals—integrated I/O processor, 4M bits
on-chip dual-ported SRAM, glueless multiprocessing fea-
tures, and ports (serial, link, external bus, and JTAG)
FEATURES
100 MHz (10 ns) core instruction rate (ADSP-21160N)
Single-cycle instruction execution, including SIMD opera-
tions in both computational units
Dual data address generators (DAGs) with modulo and bit-
reverse addressing
Zero-overhead looping and single-cycle loop setup, provid-
ing efficient program sequencing
IEEE 1149.1 JTAG standard Test Access Port and on-chip
emulation
400-ball 27 mm × 27 mm PBGA package
Available in lead-free (RoHS compliant) package
200 million fixed-point MACs sustained performance
(ADSP-21160N)
Figure 1. Functional Block Diagram
MULT
ALU
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEY)
16 x 40-BIT
MULT
ALU
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEX)
16x40-BIT
SERIAL PORTS
(2)
LINK PORTS
(6)
4
6
60
IOP
REGISTERS
(MEMORY
MAPPED)
CONTROL,
STATUS AND
DATA BUFFERS
I/O PROCESSOR
DMA
CONTROLLER
TIMER
INSTRUCTION
CACHE
32x48-BIT
ADDR
DATA
ADDR
DATA
ADDR
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
DUAL-PORTED SRAM
JTAG
TEST AND
EMULATION
6
HOST PORT
ADDR BUS
MUX
IOA
18
IOD
64
MULTIPROCESSOR
INTERFACE
EXTERNAL
PORT
DATA BUS
MUX
64
32
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
BUS
CONNECT
(PX)
DAG1
8x4 x 32
32
16/32/40/48/64
32/40/64
CORE PROCESSOR
PROGRAM
SEQUENCER
DAG2
8x 4x 32
B
L
O
C
K
0
B
L
O
C
K
1
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-21160NCB-TBD | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21160NCBZ-100 | 功能描述:IC DSP CONTROLLER 32BIT 400-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21160NCE-100 | 制造商:Analog Devices 功能描述: |
| ADSP-21160NKB-100 | 功能描述:IC DSP CONTROLLER 32BIT 400BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21160NKB-95 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
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