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參數資料
型號: ADSP-21261SKBCZ150
廠商: Analog Devices Inc
文件頁數: 1/44頁
文件大小: 0K
描述: IC DSP 32BIT 150MHZ 136-CSPBGA
產品培訓模塊: SHARC Processor Overview
標準包裝: 1
系列: SHARC®
類型: 浮點
接口: DAI,SPI
時鐘速率: 150MHz
非易失內存: ROM(384 kB)
芯片上RAM: 128kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 136-LFBGA,CSPBGA
供應商設備封裝: 136-CSPBGA(12x12)
包裝: 托盤
a
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SHARC
Embedded Processor
ADSP-21261
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
SUMMARY
High performance 32-bit/40-bit floating-point processor
Code compatibility—at assembly level, uses the same
instruction set as other SHARC DSPs
Single-instruction multiple-data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating-point computational
units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O—a parallel port, an SPI
port, four serial
ports, a digital applications interface (DAI), and JTAG
DAI incorporates two precision clock generators (PCGs), an
input data port (IDP) that includes a parallel data acquisi-
tion port (PDAP), and three programmable timers, all
under software control by the signal routing unit (SRU)
On-chip memory—1M bit of on-chip SRAM and a dedicated
3M bit of on-chip mask-programmable ROM
The ADSP-21261 is available in commercial and industrial
temperature grades. For complete ordering information,
KEY FEATURES
Serial ports offer left-justified sample-pair and I
2S support
via 12 programmable and simultaneous receive or trans-
mit pins, which support up to 24 transmit or 24 receive I2S
channels of audio when all four serial ports (SPORTs) are
enabled or six full duplex TDM streams of up to 128
channels per frame
At 150 MHz (6.67 ns) core instruction rate, the ADSP-21261
operates at 900 MFLOPS peak/600 MFLOPS sustained per-
formance whether operating on fixed- or floating-point
data
300 MMACS sustained performance at 150 MHz
Super Harvard Architecture—three independent buses for
dual data fetch, instruction fetch, and nonintrusive, zero-
overhead I/O
Transfers between memory and core at up to four 32-bit
floating- or fixed-point words per cycle, sustained
1.8G byte/s bandwidth at 150 MHz core instruction rate
and 900M byte/s is available via DMA
Figure 1. Functional Block Diagram
ADDR
DATA
PX REGI STER
6
JTAG TES T & EMULATION
20
3
SERIAL PORTS (4)
INPUT
DATA PORTS (8)
PARALLEL DATA
ACQUISITION PORT
TIMERS (3)
SI GNAL
RO UTI NG
UNI T
PRECISI ON CLOCK
GENERATORS (2)
DIGITAL APPLICATIONS INTERFACE
3
16
A DDRES S/
DATA BUS /GPIO
CON TR OL/GPIO
PARALLEL
PORT
IOP
REGISTE RS
(MEMORY MAPPED)
CO NTROL,
STATUS ,
DATA BUFFERS
4
SPI PORT (1)
DMA CONTRO LLER
18 CH ANN E LS
4
GPIO FLAGS/
IRQ /TIMEXP
PRO CESSI NG
ELEMENT
(PEY)
PROCESSING
ELEMENT
(PEX)
TIMER
INSTRUCTION
CACHE
32
48-BIT
DAG1
8
4
32
DAG2
8
4
32
PM ADDRE SS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
64
CORE PROCESSOR
PROG RAM
SEQ UE NCER
ADDR
DATA
SRAM
0.5M BI T
RO M
1.5M BIT
DUAL PORTED MEMORY
BLOCK 0
DUAL PORTED MEMORY
BLOCK 1
S
IOD
(32)
IOA
(18)
32
I/O PROCESSOR
ROM
1. 5M BIT
SRAM
0. 5M BIT
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