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參數(shù)資料
| 型號： | ADSP-21262 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | SHARC處理器 |
| 文件頁數(shù)： | 12/44頁 |
| 文件大小： | 1295K |
| 代理商： | ADSP-21262 |
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Rev. A
|
Page 12 of 44
|
May 2004
ADSP-21262
DAI_P20-1
I/O/T
Three-state with
programmable
pull-up
Digital Audio Interface Pins
. These pins provide the physical interface to the SRU.
The SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determine the exact behavior of the pin. Any input
or output signal present in the SRU may be routed to any of these pins. The SRU
provides the connection from the serial ports, input data port, precision clock gener-
ators, and timer to the DAI_P20-1 pins. These pins have internal 22.5 k
pull-up
resistors which are enabled on reset. These pull-ups can be disabled in the
DAI_PIN_PULLUP register.
Serial Peripheral Interface Clock Signal
. Driven by the master, this signal controls
the rate at which data is transferred. The master may transmit data at a variety of
baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that
is active during data transfers, only for the length of the transferred word. Slave
devices ignore the serial clock if the slave select input is driven inactive (HIGH). SPICLK
is used to shift out and shift in the data driven on the MISO and MOSI lines. The data
is always shifted out on one clock edge and sampled on the opposite edge of the
clock. Clock polarity and clock phase relative to data are programmable into the
SPICTL control register and define the transfer format. SPICLK has a 22.5 k
internal
pull-up resistor.
Serial Peripheral Interface Slave Device Select
. An active low signal used to select
the DSP as an SPI slave device. This input signal behaves like a chip select, and is
provided by the master device for the slave devices. In multimaster mode the DSP’s
SPIDS signal can be driven by a slave device to signal to the DSP (as SPI master) that
an error has occurred, as some other device is also trying to be the master device. If
asserted low when the device is in master mode, it is considered a multimaster error.
For a single-master, multiple-slave configuration where flag pins are used, this pin
must be tied or pulled high to V
DDEXT
on the master device. For ADSP-21262 to ADSP-
21262 SPI interaction, any of the master ADSP-21262's flag pins can be used to drive
the SPIDS signal on the ADSP-21262 SPI slave device.
SPI Master Out Slave In
. If the ADSP-21262 is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the ADSP-21262
is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving
input data. In an ADSP-21262 SPI interconnection, the data is shifted out from the
MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI
has a 22.5 k
internal pull-up resistor.
SPI Master In Slave Out
. If the ADSP-21262 is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the ADSP-21262 is
configured as a slave, the MISO pin becomes a data transmit (output) pin, trans-
mitting output data. In an ADSP-21262 SPI interconnection, the data is shifted out
from the MISO output pin of the slave and shifted into the MISO input pin of the
master. MISO has a 22.5 k
internal pull-up resistor. MISO can be configured as O/D
by setting the OPD bit in the SPICTL register.
Note:
Only one slave is allowed to transmit data at any given time.
To enable broadcast
transmission to multiple SPI slaves, the DSP's MISO pin may be disabled by setting
(=1) Bit 5 (DMISO) of the SPICTL register.
Boot Configuration Select
. Selects the boot mode for the DSP. The BOOTCFG pins
must be valid before reset is asserted. See
Table 4 on Page 14
for a description of the
boot modes.
SPICLK
I/O
Three-state with
pull-up enabled
SPIDS
I
Input only
MOSI
I/O (O/D)
Three-state with
pull-up enabled
MISO
I/O (O/D)
Three-state with
pull-up enabled
BOOTCFG1-0
I
Input only
Table 2. Pin Descriptions (Continued)
Pin
Type
State During and
After Reset
Function
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PDF描述 |
|---|---|
| ADSP-21262SKBC-200 | SHARC Processor |
| ADSP-21262SKBCZ200 | SHARC Processor |
| ADSP-21266 | SHARC Embedded Processor |
| ADSP-21266SKBC-2B | SHARC Embedded Processor |
| ADSP-21266SKBCZ-2B | SHARC Embedded Processor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21262_05 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Embedded Processor |
| ADSP-21262KSTZ200 | 制造商:Analog Devices 功能描述:- Trays |
| ADSP-21262SBBC-150 | 功能描述:IC DSP 32BIT 150MHZ 136-CSPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21262SBBCZ150 | 功能描述:IC DSP 32BIT 150MHZ 136-CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21262SKATZ-200 | 制造商:Analog Devices 功能描述: |
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