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參數(shù)資料
| 型號： | ADSP-21364SCSQZENG |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PQFP144 |
| 封裝： | LEAD FREE, MS-026BFB-HD, HSLQFP-144 |
| 文件頁數(shù)： | 11/52頁 |
| 文件大?。?/td> | 853K |
| 代理商： | ADSP-21364SCSQZENG |
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ADSP-21364
Preliminary Technical Data
Rev. PrB
|
Page 11 of 52
|
September 2004
PIN FUNCTION DESCRIPTIONS
ADSP-21364 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS and TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
to CLKIN (or to TCK for TRST). Tie or pull unused inputs to
V
DDEXT
or GND, except for the following:
DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI,
and AD15–0 (NOTE: These pins have pullup resistors.)
The following symbols appear in the Type column of
Table 3
:
A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
(O/D) = Open Drain, and T = Three-State, (pd) = pulldown
resistor, (pu) = pullup resistor. .
Table 3. Pin Descriptions
Pin
Type
State During &
After Reset
Three-state with
pullup enabled
Function
AD15–0
I/O/T
(pu)
Parallel Port Address/Data.
The ADSP-21364 parallel port and its corresponding
DMA unit output addresses and data for peripherals on these multiplexed pins. The
multiplex state is determined by the ALE pin. The parallel port can operate in either
8-bit or 16-bit mode. Each AD pin has a 22.5 k
internal pullup resistor. See
Address
Data Modes on Page 14
for details of the AD pin operation.
For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper
16 external address bits, A23–8; ALE is used in conjunction with an external latch to
retain the values of the A23–8.
For 16-bit mode: ALE is automatically asserted whenever a change occurs in the
address bits, A15–0; ALE is used in conjunction with an external latch to retain the
values of the A15–0. To use these pins as flags (FLAGS15–0) or PWMs (PWM15–0), 1)
set (=1) bit 20 of the SYSCTL register to disable the parallel port, 2) set (=1) bits 22–25
of the SYSCTL register to enable FLAGS in groups of four (bit 22 for FLAGS3–0, bit 23
for FLAGS7–4 etc.) or, set (=1) bits 26–29 of the SYSCTL register to enable PWMs in
groups of four (bit 26 for PWM0–3, bit 27 for PWM4–7, and so on). When used as an
input, the IDP Channel0 can use these pins for parallel input data.
Parallel Port Read Enable.
RD is asserted low whenever the processor reads 8-bit or
16-bit data from an external memory device. When AD15–0 are flags, this pin remains
deasserted. RD has a 22.5 k
internal pullup resistor.
Parallel Port Write Enable.
WR is asserted low whenever the processor writes 8-bit or
16-bit data to an external memory device. When AD15–0 are flags, this pin remains
deasserted. WR has a 22.5 k
internal pullup resistor.
Parallel Port Address Latch enable.
ALE is asserted whenever the processor drives
a new address on the parallel port address pins. On reset, ALE is active high. However,
it can be reconfigured using software to be active low. When AD15–0 are flags, this
pin remains deasserted. ALE has a 20 k
internal pulldown resistor.
Flag Pins.
Each flag pin is configured via control bits as either an input or output. As
an input, it can be tested as a condition. As an output, it can be used to signal external
peripherals. These pins can be used as an SPI interface slave select output during SPI
mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals.
In SPI master boot mode, FLAG0 is the slave select pin that must be connected to an
SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When bit 16
is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0.
When bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1.
When bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2.
When bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP which
indicates that the system timer has expired.
RD
O
(pu)
Three-state, driven
high
1
WR
O
(pu)
Three-state, driven
high
1
ALE
O
(pd)
Three-state, driven
low
1
FLAG3–0
I/O/A
Three-state
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-21364SKBC-ENG | SHARC Processor |
| ADSP-21364SKBCZENG | SHARC Processor |
| ADSP-21364SKSQ-ENG | SHARC Processor |
| ADSP-21364SKSQZENG | SHARC Processor |
| ADSP-21365SKBC-ENG | SHARC Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21364SKBC-ENG | 制造商:Analog Devices 功能描述: |
| ADSP-21364SKBCZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21364SKSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21364SKSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21364WBBCZ-1A | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
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