- 您現在的位置：買賣IC網 > PDF目錄374034 > ADSP-2161BP-66 (ANALOG DEVICES INC) DSP Microcomputers with ROM PDF資料下載
參數資料
| 型號： | ADSP-2161BP-66 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputers with ROM |
| 中文描述： | 24-BIT, 16.67 MHz, OTHER DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數： | 8/39頁 |
| 文件大?。?/td> | 243K |
| 代理商： | ADSP-2161BP-66 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁
REV. 0
ADSP-216x
–8–
ADSP-2163/ADSP-2164
When MMAP = 0, on-chip program memory ROM occupies
4K words beginning at address 0x0000. Off-chip program
memory uses the remaining 12K words beginning at address
0x1000.
When MMAP = 1, 2K words of off-chip program memory begin
at address 0x0000. 2K words of on-chip program memory ROM
is at 0x0800 to 0x0FF0, and the remainder 2K words of pro-
gram memory ROM is at 0x3800 to 0x3FFF. An additional
10K of off-chip program memory is at 0x1000 to 0x37FF.
MMAP = 0
4K
INTERNAL
ROM
RESERVED
MMAP = 1
0x0000
0x0FF0
0x0FFF
0x1000
0x3FFF
2K
EXTERNAL
RESERVED
0x0000
0x0FF0
0x0FFF
0x1000
0x3FFF
2K
INTERNAL
ROM
10K
EXTERNAL
2K
INTERNAL
ROM
0x07FF
0x0800
0x37FF
0x3800
12K
EXTERNAL
Figure 6. ADSP-2163/ADSP-2164 Program Memory Maps
Data Memory Interface
The data memory address bus (DMA) is 14 bits wide. The
bidirectional external data bus is 24 bits wide, with the upper 16
bits used for data memory data (DMD) transfers.
The data memory select (DMS) signal indicates access to data
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and can be used as a write
strobe. The read (RD) signal indicates a read operation and can
be used as a read strobe or output enable signal.
The ADSP-216x processors support memory-mapped I/O, with
the peripherals memory-mapped into the data memory address
space and accessed by the processor in the same manner as data
memory.
Data Memory Map
For the ADSP-2165/ADSP-2166, on-chip data memory RAM
resides in the 4K words beginning at address 0x2000, as shown
in Figure 7. Data memory locations from 0x3000 to the end of
data memory at 0x3FFF are reserved. Control and status regis-
ters for the system, timer, wait-state configuration, and serial port
operations are located in this region of memory.
The remaining 8K of data memory is located off-chip. This
external data memory is divided into three zones, each associ-
ated with its own wait-state generator. This allows slower pe-
ripherals to be memory-mapped into data memory for which
wait states are specified. By mapping peripherals into different
zones, you can accommodate peripherals with different wait-
state requirements. All zones default to 7 wait states after
RESET
.
0x0000
4K
3
16
MEMORY-MAPPED
REGISTERS
& RESERVED
0x0800
ADDRESS (HEX)
4K
3
16 INTERNAL
6K EXTERNAL
DWAIT2
1K EXTERNAL
DWAIT0
1K EXTERNAL
DWAIT1
0x0400
0x2000
0x3000
0x3FFF
EXTERNAL
RAM
INTERNAL
RAM
Figure 7. ADSP-2165/ADSP-2166 Data Memory Map
ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164
For the ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164, on-
chip data memory RAM resides in the 512 words beginning at
address 0x3800, also shown in Figure 8. Data memory locations
from 0x3A00 to the end of data memory at 0x3FFF are reserved.
Control and status registers for the system, timer, wait-state
configuration, and serial port operations are located in this
region of memory.
0x0000
512
ADSP-2161/62/63/64
0x0800
ADDRESS (HEX)
10K EXTERNAL
DWAIT2
1K EXTERNAL
DWAIT0
1K EXTERNAL
DWAIT1
0x0400
0x3000
0x3C00
0x3FFF
EXTERNAL
RAM
INTERNAL
RAM
1K EXTERNAL
DWAIT3
1K EXTERNAL
DWAIT4
MEMORY-MAPPED
CONTROL REGISTERS
& RESERVED
0x3A00
0x3800
0x3400
Figure 8. ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164
Data Memory Map
The remaining 14K of data memory is located off-chip. This
external data memory is divided into five zones, each associated
with its own wait-state generator. This allows slower peripherals
to be memory-mapped into data memory for which wait states
are specified. By mapping peripherals into different zones, you
can accommodate peripherals with different wait-state require-
ments. All zones default to seven wait states after
RESET
.
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-2162BS-40 | ADSP-2100 Family DSP Microcomputers |
| ADSP-2162KP-40 | DSP Microcomputers with ROM |
| ADSP-2164KP-40 | DSP Microcomputers with ROM |
| ADSP-2165KS-100 | DSP Microcomputers with ROM |
| ADSP-2165KS-80 | DSP Microcomputers with ROM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-2161BP-662 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2161BS-66 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2161BS-662 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2161KP-66 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2161KP-662 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
發布緊急采購，3分鐘左右您將得到回復。