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參數資料
型號: ADSP-2162BP-40
廠商: ANALOG DEVICES INC
元件分類: 數字信號處理
英文描述: DSP Microcomputers with ROM
中文描述: 24-BIT, 10.24 MHz, OTHER DSP, PQCC68
封裝: PLASTIC, LCC-68
文件頁數: 23/39頁
文件大小: 243K
代理商: ADSP-2162BP-40
REV. 0
ADSP-216x
–23–
TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)
INTERRUPTS AND FLAGS
16.67 MHz
Min
20 MHz
Min
25 MHz
Min
Frequency Dependency
Min
Parameter
Max
Max
Max
Max
Unit
Timing Requirements:
t
IFS
IRQx
1
or FI Setup Before
CLKOUT Low
2, 3
t
IFS
IRQx
1
or FI Setup Before
CLKOUT Low
2, 3
t
IFH
IRQx
1
or FI Hold After CLKOUT
High
2, 3
Switching Characteristics:
t
FOH
FO Hold After CLKOUT High
t
FOD
FO Delay from CLKOUT High
30
27.5
25
0.25t
CK
+ 15
ns
33
30.5
28
0.25t
CK
+ 18
ns
15
12.5
10
0.25t
CK
ns
0
0
0
0
ns
ns
15
15
12
4
15
4
NOTES
1
IRQx
=
IRQ0
,
IRQ1
, and
IRQ2
.
2
If
IRQx
and FI inputs meet t
IFS
and t
IFH
setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the
following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the
ADSP-2100 Family User’s Manual
, Third Edition
for further
information on interrupt servicing.)
3
Edge-sensitive interrupts require pulsewidths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
4
For 25 MHz only, the maximum frequency dependency for t
FOD
= 12 ns.
t
FOH
CLKOUT
FLAG
OUTPUT(S)
IRQx
FI
t
IFS
t
IFH
t
FOD
Figure 22. Interrupts and Flags
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相關代理商/技術參數
參數描述
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