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參數資料
| 型號： | ADSP-2164BP-40 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | SWITCH PB SPDT VERT .4VA SEALED |
| 中文描述： | 24-BIT, 10.24 MHz, OTHER DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數： | 16/39頁 |
| 文件大小： | 243K |
| 代理商： | ADSP-2164BP-40 |
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REV. 0
ADSP-216x
SPECIFICATIONS
ADSP-2161/ADSP-2163/ADSP-2165
–16–
TEST CONDITIONS
Figure 12 shows voltage reference levels for ac measurements.
1.5V
0.0V
OUTPUT
3.0V
INPUT
1.5V
0.8V
2.0V
Figure 12.VoltageReferenceLevels for AC Measurements
(Except Output Enable/Disable)
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured out-
put high or low voltage to a high impedance state. The output
disable time (t
DIS
) is the difference of t
MEASURED
and t
DECAY
, as
shown in Figure 13. The time t
MEASURED
is the interval from
when a reference signal reaches a high or low voltage level to
when the output voltages have changed by 0.5 V from the mea-
sured output high or low voltage.
The decay time, t
DECAY
, is dependent on the capacitative load,
C
L
, and the current load, i
L
, on the output pin. It can be ap-
proximated by the following equation:
t
C
V
i
DECAY
L
L
=
×
0 5
from which
t
DIS
=
t
MEASURED
–
t
DECAY
is calculated. If multiple pins (such as the data bus) are disabled,
the measurement value is that of the last pin to stop driving.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t
ENA
) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in Figure 13. If multiple pins (such as the data bus) are enabled,
the measurement value is that of the first pin to start driving.
2.0V
1.0V
t
ENA
REFERENCE
SIGNAL
OUTPUT
t
DECAY
V
(MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
t
DIS
t
MEASURED
V
(MEASURED)
V
OH
(MEASURED) – 0.5V
V
OL
(MEASURED) +0.5V
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
V
(MEASURED)
V
(MEASURED)
Figure 13. Output Enable/Disable
TO
OUTPUT
PIN
50pF
+1.5V
I
OH
I
OL
Figure 14. Equivalent Device Loading for AC
Measurements (Except Output Enable/Disable)
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| ADSP-2163BP-100 | RECTIFIER FAST-RECOVERY SINGLE 1.5A 100V 50A-ifsm 1V-vf 50ns 5uA-ir DO-15 1K/BULK |
相關代理商/技術參數 |
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|---|---|
| ADSP-2164BS-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
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| ADSP-2164KS-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
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| ADSP-2165BS-100 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputers with ROM |
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