- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374035 > ADSP-2181 (Analog Devices, Inc.) ADSP-2100 Family DSP Microcomputers PDF資料下載
參數(shù)資料
| 型號： | ADSP-2181 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ADSP-2100 Family DSP Microcomputers |
| 中文描述： | 的ADSP - 2100系列DSP的微機 |
| 文件頁數(shù)： | 3/32頁 |
| 文件大小： | 290K |
| 代理商： | ADSP-2181 |
第1頁第2頁當前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
ADSP-2181
–3–
REV. D
ADSP-2181 can fetch an operand from program memory and
the next instruction in the same cycle.
In addition to the address and data bus for external memory
connection, the ADSP-2181 has a 16-bit Internal DMA port
(IDMA port) for connection to external systems. T he IDMA
port is made up of 16 data/address pins and five control pins.
T he IDMA port provides transparent, direct access to the DSPs
on-chip program and data RAM.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). T he BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
T he byte memory and I/O memory space interface supports slow
memories and I/O memory-mapped peripherals with program-
mable wait state generation. External devices can gain control of
external buses with bus request/grant signals (
BR
,
BGH
and
BG
).
One execution mode (Go Mode) allows the ADSP-2181 to con-
tinue running from on-chip memory. Normal execution mode
requires the processor to halt while buses are granted.
T he ADSP-2181 can respond to 13 possible interrupts, eleven
of which are accessible at any given time. T here can be up to six
external interrupts (one edge-sensitive, two level-sensitive and
three configurable) and seven internal interrupts generated by
the timer, the serial ports (SPORT s), the Byte DMA port and
the power-down circuitry. T here is also a master
RESET
signal.
T he two serial ports provide a complete synchronous serial inter-
face with optional companding in hardware and a wide variety of
framed or frameless data transmit and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
T he ADSP-2181 provides up to 13 general-purpose flag pins.
T he data input and output pins on SPORT 1 can be alternatively
configured as an input flag and an output flag. In addition, there
are eight flags that are programmable as inputs or outputs and
three flags that are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (T COUNT ) is decremented every
n
pro-
cessor cycles, where
n
is a scaling value stored in an 8-bit regis-
ter (T SCALE). When the value of the count register reaches
zero, an interrupt is generated and the count register is reloaded
from a 16-bit period register (T PERIOD).
Serial Ports
T he ADSP-2181 incorporates two complete synchronous serial
ports (SPORT 0 and SPORT 1) for serial communications and
multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2181 SPORTs.
Refer to the
ADSP-2100 Family User’s Manual, Third Edition
for
further details.
SPORT s are bidirectional and have a separate, double-
buffered transmit and receive section.
SPORT s can use an external serial clock or generate their
own serial clock internally.
SPORT s have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
OUTPUT REGS
ALU
OUTPUT REGS
MAC
TIMER
INPUT REGS
INPUT REGS
ADSP-2181 INTEGRATION
AD#1
DATA
ADDRESS
GEN#2
21xx CORE
PMA BUS
DMA BUS
PMD BUS
IREGISTER
PROGRAM
EXBUS
DMD BUS
PROGRAM
1SRAM
3
24
DATA
16K
3
16
BYTE
CONDMA
MUX
14
14
24
16
DMD
BUS
PMA BUS
DMA BUS
PMD BUS
INPUT REGS
SHIFTER
OUTPUT REGS
R BUS
16
TRANSMIT REG
RECEIVE REG
SERIAL
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
COMPANDING
CIRCUITRY
5
5
INDMA
PORT
INTERRUPTS
DOWN
CLOGIC
2
8
3
MUX
PROGRAMMABLE
I/O
FLAGS
14
ADDRESS
BUS
EXTERNAL
BUS
16
4
24
Figure 1. ADSP-2181 Block Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-2181BST-115 | DSP Microcomputer |
| ADSP-2181BST-133 | DSP Microcomputer |
| ADSP2181 | DSP Microcomputer |
| ADSP-2183KST-115 | DSP Microcomputer |
| ADSP-2183KST-133 | DSP Microcomputer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-2181BS-115 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 28.8MHz 28.8MIPS 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:DSP W/LARGE RAM, 28.8MIPS I GRDE, PQFP - Bulk |
| ADSP-2181BS-133 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 33.3MHz 33.3MIPS 128-Pin MQFP 制造商:Analog Devices 功能描述:IC MICROCOMPUTER DSP |
| ADSP-2181BS-160 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| ADSP2181BST115 | 制造商:AD 功能描述:2181 ANALOG |
| ADSP-2181BST-115 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 28.8MHz 28.8MIPS 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:DSP W/LARGE RAM, 28.8MIPS I GRDE, TQFP - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。