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參數資料
| 型號： | ADSP-2184 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LM2941/LM2941C 1A Low Dropout Adjustable Regulator; Package: TO-263; No of Pins: 5; Qty per Container: 45; Container: Rail |
| 中文描述： | DSP的微機 |
| 文件頁數： | 4/31頁 |
| 文件大小： | 216K |
| 代理商： | ADSP-2184 |
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ADSP-2184L
–4–
REV. 0
Common-Mode Pins
#
of
Pins put
1
1
1
1
1
1
1
1
1
1
1
1
Input/
Out-
Pin
Name(s)
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2/
Function
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive
Interrupt Request
1
Programmable I/O Pin
Level-Sensitive Interrupt Requests
1
Programmable I/O Pin
Level-Sensitive Interrupt Requests
1
Programmable I/O Pin
Edge-Sensitive Interrupt Requests
1
Programmable I/O Pin
Programmable I/O Pin
Mode Select Input—Checked
only During
RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
only During
RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
only During
RESET
Programmable I/O Pin During
Normal Operation
Clock or Quartz Crystal Input
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts,
Flag In, Flag Out
2
Power-Down Control Input
Power-Down Control Output
Output Flags
Power and Ground
For Emulation Use
3
I
I
O
O
O
O
I/O
O
O
O
O
I
PF7
IRQL0/
PF5
IRQL1/
PF6
IRQE/
PF4
PF3
Mode C/
I/O
I
I/O
I
I/O
I
I/O
I/O
I
1
1
1
1
1
PF2
I/O
Mode B/
1
I
PF1
I/O
Mode A/
1
I
PF0
I/O
CLKIN, XTAL 2
CLKOUT
SPORT0
SPORT1
IRQ1:0
/
FI, FO
PWD
PWDACK
FL0, FL1, FL2 3
V
DD
and GND
EZ-Port
I
O
I/O
I/O
1
5
5
1
1
I
O
O
I
I/O
16
9
NOTES
1
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to
enable the corresponding interrupts, the DSP will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices or
set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Soft-
ware configurable.
3
See Designing an EZ-ICE-Compatible System in this data sheet for complete
information.
Memory Interface Pins
The ADSP-2184L processor can be used in one of two modes:
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode, which
allows IDMA operation with limited external addressing capabili-
ties. The operating mode is determined by the state of the Mode C
pin during reset and cannot be changed while the processor is
running. (See Table VI for complete mode operation descriptions.)
Full Memory Mode Pins (Mode C = 0)
#
of
Input/
Pin Name
Pins
Output
Function
A13:0
14
O
Address Output Pins for Pro-
gram, Data, Byte and I/O Spaces
Data I/O Pins for Program,
Data, Byte and I/O Spaces
(8 MSBs Are Also Used as
Byte Memory Addresses)
D23:0
24
I/O
Host Mode Pins (Mode C = 1)
#
of
Pin Name
Pins
Input/
Output
Function
IAD15:0
A0
16
1
I/O
O
IDMA Port Address/Data Bus
Address Pin for External I/O,
Program, Data or Byte Access
Data I/O Pins for Program,
Data Byte and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge
D23:8
16
I/O
IWR
IRD
IAL
IS
IACK
1
1
1
1
1
I
I
I
I
O
In Host Mode, external peripheral addresses can be decoded using the A0,
BMS
,
CMS
,
PMS
,
DMS
and
IOMS
signals.
Setting Memory Mode
Memory Mode selection for the ADSP-2184L is made during
chip reset through the use of the Mode C pin. This pin is multi-
plexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are passive and active.
Passive configuration involves the use of a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 k
, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as a
programmable flag output without undue strain on the processor’s
output driver. For minimum power consumption during
power-down, reconfigure PF2 to be an input, as the pull-up or
pull-down will hold the pin in a known state, and will not switch.
Active configuration involves the use of a three-stateable exter-
nal driver connected to the Mode C pin. A driver’s output en-
able should be connected to the DSP’s
RESET
signal such that
it only drives the PF2 pin when
RESET
is active (low). After
RESET
is deasserted, the driver should three-state, thus allow-
ing full use of the PF2 pin as either an input or output.
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