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參數資料
| 型號： | ADSP-2184BST-160 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 24-BIT, 40 MHz, OTHER DSP, PQFP100 |
| 封裝： | METRIC, PLASTIC, TQFP-100 |
| 文件頁數： | 6/31頁 |
| 文件大小： | 216K |
| 代理商： | ADSP-2184BST-160 |
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ADSP-2184L
–6–
REV. 0
Idle
When the ADSP-2184L is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the IDLE instruction.
In Idle mode IDMA, BDMA and autobuffer cycle steals still
occur.
Slow Idle
The IDLE instruction is enhanced on the ADSP-2184L to let
the processor’s internal clock signal be slowed, further reducing
power consumption. The reduced clock frequency, a program-
mable fraction of the normal clock rate, is specified by a select-
able divisor given in the IDLE instruction. The format of the
instruction is:
IDLE (n)
where
n
= 16, 32, 64 or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals such
as SCLK, CLKOUT and timer clock, are reduced by the same
ratio. The default form of the instruction, when no clock divisor
is given, is the standard IDLE instruction.
When the
IDLE (n)
instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts. The one-cycle response time of the standard
idle state is increased by
n
, the clock divisor. When an enabled
interrupt is received, the ADSP-2184L will remain in the idle
state for up to a maximum of
n
processor cycles (
n
= 16, 32, 64
or 128) before resuming normal operation.
When the
IDLE (n)
instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced due to the additional time the
processor takes to come out of the idle state (a maximum of
n
processor cycles).
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-2184L, two serial devices, a byte-wide EPROM and op-
tional external program and data overlay memories (mode select-
able). Programmable wait state generation allows the processor
to connect easily to slow peripheral devices. The ADSP-2184L
also provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode
allows access to the full external data bus, but limits addressing
to a single address bit (A0). Additional system peripherals can
be added in this mode through the use of external hardware to
generate and latch address signals.
1/2xOR
CRYSTAL
SERIAL
SERIAL
SCLK1
RFS1 OR
IRQ0
IRQ1
TFS1 OR
SCLK0
SPORT0
A0-A21
DATA
CS
BYTE
MEMORY
I/O SPACE
(PERIPHERALS)
2048 LOCATIONS
CS
DATA
ADDR
DATA
ADDR
OVERLAY
MEMORY
PMTWO 8K
DTWO 8K
D
23-0
A
13-0
D
23-8
A
10-0
D
15-8
D
23-16
A
13-0
14
24
FL0-2
PF3
CLKIN
XTAL
ADDR13-0
DATA23-0
BMS
IOMS
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
ADSP-2184L
1/2x CLOCK
OR
CRYSTAL
SERIAL
SERIAL
ISYOR
m
CONTROLLER
16
1
16
SCLK0
RFS0
TFS0
DT0
DR0
/D6
IRD
/D7
IS
IACK
/D3
IAD15-0
IDMA PORT
FL0-2
PF3
CLKIN
XTAL
A0
DATA23-8
BMS
IOMS
PMS
DMS
BBR
PWD
PWDACK
ADSP-2184L
IRQ2
/PF7
//PF5
IRQE
/PF6
MODE C/PF2
MODE B/PF1
MODE A/PF0
HOST MEMORY MODE
IRQ2
/PF7
IRQE
/PF4
IRQL0
/PF5
IRQL1
/PF6
MODE C/PF2
MODE B/PF1
MODE A/PF0
FULL MEMORY MODE
WR
RD
WR
RD
SCLK1
IRQ0
DT1 OR FO
Figure 2. Basic System Configuration
相關PDF資料 |
PDF描述 |
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| ADSP-2184L | LM2941/LM2941C 1A Low Dropout Adjustable Regulator; Package: TO-220; No of Pins: 5; Qty per Container: 45; Container: Rail |
| ADSP-2184NKST-320 | DSP Microcomputer |
| ADSP-2186NKCA-320 | DSP Microcomputer |
| ADSP-2184N | DSP Microcomputer |
| ADSP-2187N | DSP Microcomputer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-2184BSTZ-160 | 功能描述:IC DSP CONTROLLER 16BIT 100LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:ADSP-21xx 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-2184BSTZ-160 | 制造商:Analog Devices 功能描述:Digital Signal Processor IC |
| ADSP-2184L | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-2184LBST-160 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 40MHz 40MIPS 100-Pin LQFP 制造商:Analog Devices 功能描述:IC MICROCOMPUTER 16-BIT |
| ADSP-2184LBSTZ-160 | 功能描述:IC DSP CONTROLLER 16BIT 100LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:ADSP-21xx 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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