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參數資料
| 型號： | ADSP-2185LKST-210 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 24-BIT, 26.3 MHz, OTHER DSP, PQFP100 |
| 封裝： | MS-026BED, LQFP-100 |
| 文件頁數： | 4/31頁 |
| 文件大小： | 223K |
| 代理商： | ADSP-2185LKST-210 |
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REV. A
ADSP-2185L
–4–
Common-Mode Pin Descriptions
Pin
Name(s)
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2/
PF7
IRQL1/
PF6
IRQL0/
PF5
IRQE/
PF4
PF3
# of
Pins Output
1
I
1
I
1
O
1
O
1
O
1
O
1
O
1
O
1
O
1
O
1
O
1
I
I/O
1
I
I/O
1
I
I/O
1
I
I/O
I/O
Input/
Function
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive Interrupt
Request.
1
Programmable I/O Pin
Level-Sensitive Interrupt Requests
1
Programmable I/O Pin
Level-Sensitive Interrupt Requests
1
Programmable I/O Pin
Edge-Sensitive Interrupt Requests
1
Programmable I/O Pin
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
Only During
RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
Only During
RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
Only During
RESET
Programmable I/O Pin During
Normal Operation
Mode C/
1
I
PF2
I/O
Mode B/
1
I
PF1
I/O
Mode A/
1
I
PF0
I/O
CLKIN,
XTAL
CLKOUT
SPORT0
SPORT1
IRQ1:0
FI, FO
PWD
PWDACK
FL0, FL1,
FL2
VDD and
GND
EZ-Port
2
1
5
5
I
O
I/O
I/O
Clock or Quartz Crystal Input
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts,
Flag In, Flag Out
2
Power-Down Control Input
Power-Down Control Output
1
1
I
O
3
O
Output Flags
16
9
I
I/O
Power and Ground
For Emulation Use
N
OTES
1
Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the
corresponding interrupts, then the DSP will vector to the appropriate interrupt vec-
tor address when the pin is asserted, either by external devices, or set as a program-
mable flag.
2
SPORT configuration determined by the DSP System Control Register. Software
configurable.
Memory Interface Pins
The ADSP-2185L processor can be used in one of two modes,
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. The operating mode is determined by the state of
the Mode C pin during
RESET
and cannot be changed while
the processor is running. See tables for Full Memory Mode Pins
and Host Mode Pins for descriptions.
Full Memory Mode Pins (Mode C = 0)
Pin
Name(s) Pins Output Function
A13:0
14
O
# of
Input/
Address Output Pins for Program,
Data, Byte and I/O Spaces
Data I/O Pins for Program, Data,
Byte and I/O Spaces (8 MSBs are
also used as Byte Memory addresses)
D23:0
24
I/O
Host Mode Pins (Mode C = 1)
Pin
Name(s) Pins Output Function
IAD15:0 16
I/O
A0
1
O
# of
Input/
IDMA Port Address/Data Bus
Address Pin for External I/O, Pro-
gram, Data or Byte access
Data I/O Pins for Program, Data
Byte and I/O spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge
D23:8
16
I/O
IWR
IRD
IAL
IS
IACK
1
1
1
1
1
I
I
I
I
O
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS
,
PMS
,
DMS
and
IOMS
signals
Terminating Unused Pin
The following table shows the recommendations for terminating
unused pins.
Pin Terminations
I/O
3-State
(Z)
Hi-Z*
Caused
By
Pin
Name
Reset
State
Unused
Configuration
XTAL
CLKOUT
A13:1 or
IAD12:0
A0
D23:8
D7 or
IWR
D6 or
IRD
D5 or
IAL
I
O
O (Z)
I/O (Z)
O (Z)
I/O (Z)
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
I
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I
Hi-Z
I
Hi-Z
I
Float
Float
Float
Float
Float
Float
Float
High (Inactive)
Float
High (Inactive)
Float
Low (Inactive)
BR
,
EBR
IS
BR
,
EBR
BR
,
EBR
BR
,
EBR
BR
,
EBR
BR
,
EBR
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