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| 型號(hào)： | ADSP-2188 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無(wú)電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù) |
| 文件頁(yè)數(shù)： | 5/48頁(yè) |
| 文件大小： | 1571K |
| 代理商： | ADSP-2188 |
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–5–
REV. 0
ADSP-218xN Series
Table 2. Common-Mode Pins
Pin Name
# of Pins
I/O
Function
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
1
1
1
1
1
1
1
1
I
I
O
O
O
O
O
O
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
CMS
RD
WR
IRQ2
PF7
IRQL1
PF6
IRQL0
PF5
IRQE
PF4
Mode D
PF3
Mode C
PF2
Mode B
PF1
Mode A
PF0
CLKIN
XTAL
CLKOUT
SPORT0
SPORT1
IRQ1–0, FI, FO
PWD
PWDACK
FL0, FL1, FL2
V
DDINT
V
DDEXT
GND
V
DDINT
V
DDEXT
1
1
1
1
O
O
O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
O
O
I/O
I/O
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive Interrupt Request
1
Programmable I/O pin
Level-Sensitive Interrupt Requests
1
Programmable I/O Pin
Level-Sensitive Interrupt Requests
1
Programmable I/O Pin
Edge-Sensitive Interrupt Requests
1
Programmable I/O Pin
Mode Select Input—Checked Only During RESET
Programmable I/O Pin During Normal Operation
Mode Select Input—Checked Only During RESET
Programmable I/O Pin During Normal Operation
Mode Select Input—Checked Only During RESET
Programmable I/O Pin During Normal Operation
Mode Select Input—Checked Only During RESET
Programmable I/O Pin During Normal Operation
Clock Input
Quartz Crystal Output
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts, FI, FO
2
Power-Down Control Input
Power-Down Acknowledge Control Output
Output Flags
Internal V
DD
(1.8 V) Power (LQFP)
External V
DD
(1.8 V, 2.5 V, or 3.3 V) Power (LQFP)
Ground (LQFP)
Internal V
DD
(1.8 V) Power (Mini-BGA)
External V
DD
(1.8 V, 2.5 V, or 3.3 V) Power (Mini-
BGA)
Ground (Mini-BGA)
For Emulation Use
1
1
1
1
1
1
1
1
1
1
5
5
1
1
3
2
4
10
4
7
I
O
O
I
I
I
I
I
GND
EZ-Port
20
9
I
I/O
1
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will
vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable
flag.
2
SPORT configuration determined by the DSP System Control Register. Software configurable.
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