參數資料
| 型號： | ADSP-21992YBC |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 1/60頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CTLR 16BIT 196CSPBGA |
| 標準包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | SPI，SSP |
| 時鐘速率： | 150MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 128kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-BGA |
| 供應商設備封裝： | 196-MBGA（15x15） |
| 包裝： | 托盤 |
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Mixed-Signal DSP Controller with CAN
ADSP-21992
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.326.3113
2007 Analog Devices, Inc. All rights reserved.
FEATURES
ADSP-2199x, 16-bit, fixed-point DSP core with up to 160
MIPS sustained performance
48K words of on-chip RAM, as 32K words on-chip 24-bit pro-
gram RAM, and 16K words on-chip, 16-bit data RAM
External memory interface
Dedicated memory DMA controller for data/instruction
transfer between internal/external memory
Programmable PLL and flexible clock generation circuitry
enables full-speed operation from low speed
input clocks
IEEE JTAG Standard 1149.1 test access port supports on-chip
emulation and system debugging
8-channel, 14-bit analog-to-digital converter system, with up
to 20 MSPS sampling rate (at 160 MHz core clock rate)
3-phase 16-bit center based PWM generation unit with 12.5
ns resolution at 160 MHz core clock (CCLK) rate
Dedicated 32-bit encoder interface unit with companion
encoder event timer
Dual 16-bit auxiliary PWM
outputs
16 general-purpose flag I/O pins
3 programmable 32-bit interval timers
SPI communications port with master or slave operation
Synchronous serial communications port (SPORT) capable of
software UART emulation
Controller area network (CAN) module, fully compliant with
V2.0B standard
Integrated watchdog timer
Dedicated peripheral interrupt controller with software
priority control
Multiple boot modes
Precision 1.0 V voltage reference
Integrated power-on-reset (POR) generator
Flexible power management with selectable power-down
and idle modes
2.5 V internal operation with 3.3 V I/O
Operating temperature ranges of –40 C to +85 C and –40 C
to +125 C
Figure 1. Functional Block Diagram
ADC
CONTROL
VREF
PIPELINE
FLASH ADC
CLOCK
GENERATOR/PLL
PM ADDRESS/DATA
DM ADDRESS/DATA
I/O
BUS
16K
16
DM RAM
32K
24
PM RAM
EXTERNAL
MEMORY
INTERFACE
(EMI)
TIMER 0
TIMER 1
TIMER 2
PM ROM
ADSP-219x
DSP CORE
JTAG
TEST AND
EMULATION
ADDRESS
DATA
CONTROL
I/O REGISTERS
PWM
GENERATION
UNIT
ENCODER
INTERFACE
UNIT
(AND EET)
AUXILIARY
PWM
UNIT
FLAG
I/O
SPI
SPORT
WATCHDOG
TIMER
INTERRUPT
CONTROLLER
(ICNTL)
POR
MEMORY DMA
CONTROLLER
CONTROLLER AREA
NETWORK (CAN)
4K
24
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