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| 型號(hào)： | ADSP2183 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS Hex Schmitt Triggers 14-TSSOP -55 to 125 |
| 中文描述： | DSP的微機(jī) |
| 文件頁(yè)數(shù)： | 15/31頁(yè) |
| 文件大小： | 252K |
| 代理商： | ADSP2183 |
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ADSP-2183
–15–
REV. C
Parameter
Min
Max
Unit
Bus Request–Bus Grant
Timing Requirements
:
t
BH
t
BS
BR
Hold after CLKOUT High
1
BR
Setup before CLKOUT Low
1
0.25t
CK
+ 2
0.25t
CK
+ 17
ns
ns
Switching Characteristics
:
t
SD
CLKOUT High to
xMS
,
RD
,
WR
Disable
xMS
,
RD
,
WR
Disable to
BG
Low
BG
High to
xMS
,
RD
,
WR
Enable
xMS
,
RD
,
WR
Enable to CLKOUT High
xMS
,
RD
,
WR
Disable to
BGH
Low
2
BGH
High to
xMS
,
RD
,
WR
Enable
2
0.25t
CK
+ 10
ns
t
SDB
0
ns
t
SE
0
ns
t
SEC
0.25t
CK
– 4
ns
t
SDBH
0
ns
t
SEH
0
ns
NOTES
xMS
=
PMS
,
DMS
,
CMS
,
IOMS
,
BMS
.
1
BR
is an asynchronous signal. If
BR
meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the
ADSP-2100 Family User’s Manual,
Third Edition
,
for
BR
/
BG
cycle relationships.
2
BGH
is asserted when the bus is granted and the processor requires control of the bus to continue.
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
SDBH
t
SEH
t
BS
BR
t
BH
CLKOUT
PMS,
DMS
BMS
,
RD
WR
BG
BGH
Figure 10. Bus Request–Bus Grant
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