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參數資料
| 型號： | ADSP2185 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | DSP微機 |
| 文件頁數： | 11/32頁 |
| 文件大小： | 289K |
| 代理商： | ADSP2185 |
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ADSP-2185
–11–
REV. 0
BIASE D ROUNDING
A mode is available on the ADSP-2185 to allow biased round-
ing in addition to the normal unbiased rounding. When the
BIASRND bit is set to 0, the normal unbiased rounding opera-
tions occur. When the BIASRND bit is set to 1, biased round-
ing occurs instead of the normal unbiased rounding. When
operating in biased rounding mode all rounding operations with
MR0 set to 0x8000 will round up, rather than only rounding up
odd MR1 values.
For example:
T able VII.
MR Value
Before RND
Biased
RND Result
Unbiased
RND Result
00-0000-8000
00-0001-8000
00-0000-8001
00-0001-8001
00-0000-7FFF
00-0001-7FFF
00-0001-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
00-0000-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
T his mode only has an effect when the MR0 register contains
0x8000; all other rounding operations work normally. T his
mode allows more efficient implementation of bit-specified
algorithms that use biased rounding, for example the GSM
speech compression routines. Unbiased rounding is preferred
for most algorithms.
Note: BIASRND bit is Bit 12 of the SPORT 0 Autobuffer Con-
trol register.
Instruction Set Description
T he ADSP-2185 assembly language instruction set has an alge-
braic syntax that was designed for ease of coding and readabil-
ity. T he assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:
T he algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX 0 + AY0, resembles a simple
equation.
Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
T he syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to use on-chip memory and conform to the ADSP-
2185’s interrupt vector and reset vector map.
Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
I/O Space Instructions
T he instructions used to access the ADSP-2185’s I/O memory
space are as follows:
Syntax:
IO(
addr
) =
dreg
dreg
= IO(
addr
);
where
addr
is an address value between 0 and 2047 and
dreg
is
any of the 16 data registers.
E xamples:
IO(23) = AR0;
AR1 = IO(17);
Description:
T he I/O space read and write instructions move
data between the data registers and the I/O
memory space.
DE SIGNING AN E Z-ICE
*-COMPAT IBLE SY ST E M
T he ADSP-2185 has on-chip emulation support and an
ICE-Port *, a special set of pins that interface to the EZ-ICE
*.
T hese features allow in-circuit emulation without replacing the
target system processor by using only a 14-pin connection from
the target system to the EZ-ICE
*. T arget systems must have a
14-pin connector to accept the EZ-ICE
*’s in-circuit probe, a
14-pin plug. See the
ADSP-2100 Family EZ-Tools
data sheet for
complete information on ICE products.
T he ICE-Port * interface consists of the following ADSP-2185
pins:
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
EE
T hese ADSP-2185 pins must be connected only to the EZ-ICE
*
connector in the target system. T hese pins have no function
except during emulation, and do not require pull-up or pull-down
resistors. T he traces for these signals between the ADSP-2185
and the connector must be kept as short as possible, no longer
than three inches.
T he following pins are also used by the EZ-ICE
*:
BR
BG
RESET
GND
T he EZ-ICE
* uses the EE (emulator enable) signal to take
control of the ADSP-2185 in the target system. T his causes the
processor to use its
ERESET
,
EBR
and
EBG
pins instead of the
RESET
,
BR
and
BG
pins. T he
BG
output is three-stated.
T hese signals do not need to be jumper-isolated in your system.
T he EZ-ICE
* connects to your target system via a ribbon cable
and a 14-pin female plug. T he female plug is plugged onto the
14-pin connector (a pin strip header) on the target board.
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相關代理商/技術參數 |
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| ADSP-2185 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-2185BST-115 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 28.8MHz 28.8MIPS 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:DSP,5V,28MHZ,32K WORD RAM, 100TQFP - Bulk |
| ADSP-2185BST-133 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 33.3MHz 33.3MIPS 100-Pin LQFP 制造商:Analog Devices 功能描述:IC MICROCOMPUTER 32-BIT 制造商:Analog Devices 功能描述:DIGITAL SIGNAL PROCESSOR IC, DSP Type:Floating Point, Package / Case:100-TQFP, S |
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| ADSP-2185BSTZ-133 | 制造商:Analog Devices 功能描述:IC 16-BIT MICROCOMPUTER |
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