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參數資料
| 型號： | ADSQ-1410S |
| 廠商： | MURATA POWER SOLUTIONS INC |
| 元件分類： | ADC |
| 中文描述： | QUAD 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, DMA66 |
| 封裝： | TDIP-66 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 541K |
| 代理商： | ADSQ-1410S |
MDA_ADSQ1410S_A03
Page 1 of 6
ADSQ-1410S
Quad 14-Bit, 10MPS Sampling
A/D Converter
www.murata-ps.com
Technical enquiries email:
sales@murrata-ps.com, tell: +1 508 339 3000
FEATURES
Quad 14-bit resolution; 10MSPS sampling rate
Functionally complete; ±2.5V input range
Low noise; No missing codes
Edge-triggered
3 latency delays
±5V and +3.3V supplies
66-pin TDIP package
Ideal for both time and frequency
domain applications
The low-cost ADSQ-1410S is a Quad 10MSPS
sampling A/D. This device has been optimized for
imaging applications so as to provide lowest noise
performance while being able to convert full-scale
step input signals at 10MHz rate. This device is
also capable of accurately sampling full-scale input
signals up to Nyquist frequencies with no missing
codes.
The ADSQ-1410S has a single, rising-edge trig-
gered, Start Convert pin to control the conversion
cycles of all four A/Ds. This device internally con-
figures the outputs of the A/Ds into pairs to provide
two parallel, 3-state, output buses. Four indepen-
dent Enable Control pins are provide for individual
output data selection. Each channel is capable of
independent offset adjustment.
Packaged in a 66 pin TDIP, the functionally
complete ADSQ-1410S contains four independent
multistage A/D converters with low-noise track-
and-hold amplifiers to assure no missing codes.
A 2.5V internal reference is provided as well as
a range selection feature that allows the user
to simultaneously adjust the input range of
all four A/Ds.
Requiring only ±5V and +3.3V supplies, the
ADSQ-1410S has a typical power dissipation of
3.1 Watts. The device is designed for a ±2.5V input
range when Range is connected to 2.5V Reference.
Typical applications include medical imaging, radar,
sonar, communications and instrumentation.
PRODUCT OVERVIEW
FUNCTIONAL BLOCK DIAGRAM
PRELIMINARY
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