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參數資料
型號: ADT7310TRZ
廠商: Analog Devices Inc
文件頁數: 20/24頁
文件大小: 393K
描述: IC TEMP SENSOR 16BIT SPI 8SOIC
標準包裝: 98
功能: 溫度監控系統(傳感器)
傳感器類型: 內部
感應溫度: -55°C ~ 150°C
精確度: ±0.5°C
拓撲: ADC(三角積分型),振蕩器,寄存器庫
輸出類型: SPI?
輸出警報:
輸出風扇:
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -55°C ~ 150°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SO
包裝: 管件
產品目錄頁面: 798 (CN2011-ZH PDF)
ADT7310
Data Sheet
 
Rev. A | Page 20 of 24
C3
C2
C5
C4
DIN
C7
C6
C1
D2
D1
D0
C0
16-BIT DATA
5
24
6
7
8
9
10
11
12
13
14
15
16
22
23
CLK
1
2
3
4
D14    D13
17
CS
R/W
REGISTER ADDR
0
0
0
CONT
READ
D12    D11    D10
D9
D8
D7
D15
OUT
8-BIT COMMAND BYTE
 
Figure 21. Read from a 16-Bit Register
 
READING DATA
A read transaction begins when the master writes the command
byte to the ADT7310 with the read/write bit set to 1. The master
then supplies 8 or 16 clock pulses, depending on the addressed
register, and the ADT7310 clocks out data from the addressed
register on the DOUT line. Data is clocked out on the first
falling edge of SCLK following the command byte.
The read transaction finishes when the master takes
CS
 high.
The master must begin a new read transaction on the bus for
every register read. Only one register is read per bus transaction.
However, in continuous read mode, Command Byte C2 = 1, and
the temperature value register can be read from continuously.
The master sends 16 clock pulses on SCLK, and the temperature
value is clocked out on DOUT.
INTERFACING TO DSPs OR MICROCONTROLLERS
The ADT7310 can be operated with CS
 used as a frame syn-
chronization signal. This scheme is useful for DSP interfaces.
In this case, the first bit (MSB) is effectively clocked out by
CS
 
because
CS
 normally occurs after the falling edge of SCLK in
DSPs. SCLK can continue to run between data transfers,
provided that the timing numbers are obeyed.
CS
 can be tied to ground, and the serial interface can be
operated in a 3-wire mode. DIN, DOUT, and SCLK are
used to communicate with the ADT7310 in this mode.
For microcontroller interfaces, it is recommended that SCLK
idle high between data transfers.
SERIAL INTERFACE RESET
The serial interface can be reset by writing a series of 1s on the
DIN input. If a Logic 1 is written to the ADT7310 line for at
least 32 serial clock cycles, the serial interface is reset. This
ensures that the interface can be reset to a known state if the
interface gets lost due to a software error or some glitch in the
system. Reset returns the interface to the state in which it is
expecting a write to the communications register. This opera-
tion resets the contents of all registers to their power-on values.
Following a reset, the user should allow a period of 500 祍
before addressing the serial interface.
 
 
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