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參數資料
| 型號： | ADT7461AR-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | 【1∑C Temperature Monitor with Series Resistance Cancellation |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | MS-012-AA, SOIC-8 |
| 文件頁數： | 14/24頁 |
| 文件大小： | 854K |
| 代理商： | ADT7461AR-REEL |
ADT7461
Table 12. List of ADT7461 Registers
Read Address (Hex)
Not Applicable
00
01
02
03
04
05
06
07
08
Not Applicable
10
11
12
13
14
19
20
21
22
FE
FF
*Writing to address 0F causes the ADT7461 to perform a single measurement. It is not a data register as such and it does not matter what data is written to it.
Write Address (Hex)
Not Applicable
Not Applicable
Not Applicable
Not Applicable
09
0A
0B
0C
0D
0E
0F
Not Applicable
11
12
13
14
19
20
21
22
Not Applicable
Not Applicable
Name
Address Pointer
Local Temperature Value
External Temperature Value High Byte
Status
Configuration
Conversion Rate
Local Temperature High Limit
Local Temperature Low Limit
External Temperature High Limit High Byte
External Temperature Low Limit High Byte
One-Shot
External Temperature Value Low Byte
External Temperature Offset High Byte
External Temperature Offset Low Byte
External Temperature High Limit Low Byte
External Temperature Low Limit Low Byte
External THERM Limit
Local THERM Limit
THERM Hysteresis
Consecutive ALERT
Manufacturer ID
Die Revision Code
Power-On Default
Undefined
0000 0000 (0×00)
0000 0000 (0×00)
Undefined
0000 0000 (0×00)
0000 1000 (0×08)
0101 0101 (0×55) (85°C)
0000 0000 (0×00) (0°C)
0101 0101 (0×55) (85°C)
0000 0000 (0×00) (0°C)
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0110 1100 (0×55) (85°C)
0101 0101 (0×55) (85°C)
0000 1010 (0×0A) (10°C)
0000 0001 (0×01)
0100 0001 (0×41)
0101 0001 (0×51)
SERIAL BUS INTERFACE
Control of the ADT7461 is carried out via the serial bus. The
ADT7461 is connected to this bus as a slave device, under the
control of a master device.
The ADT7461 has an SMBus timeout feature. When this is en-
abled, the SMBus will timeout after typically 25 ms of no activ-
ity. However, this feature is not enabled by default. Bit 7 of the
consecutive alert register (Address = 0×22) should be set to
enable it.
The ADT7461 supports packet error checking (PEC) and its use
is optional. It is triggered by supplying the extra clock for the
PEC byte. The PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial
( )
1
1
2
8
+
+
+
=
x
x
x
C
Consult the SMBus 1.1 specification for more information
(www.smbus.org).
ADDRESSING THE DEVICE
In general, every SMBus device has a 7-bit device address,
except for some devices that have extended, 10-bit addresses.
When the master device sends a device address over the bus, the
slave device with that address will respond. The ADT7461 is
available with one device address, 0×4C (1001 100b).
The serial bus protocol operates as follows:
1.
The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDATA, while the serial clock line SCLK remains
high. This indicates that an address/data stream will follow.
All slave peripherals connected to the serial bus respond to
the START condition and shift in the next eight bits, con-
sisting of a 7-bit address (MSB first) plus an R/W bit,
which determines the direction of the data transfer, i.e.,
whether data will be written to or read from the slave
device. The peripheral whose address corresponds to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known
as the Acknowledge Bit. All other devices on the bus now
remain idle while the selected device waits for data to be
read from or written to it. If the R/W bit is a 0, the master
will write to the slave device. If the R/W bit is a 1, the mas-
ter will read from the slave device.
2.
Data is sent over the serial bus in a sequence of nine clock
pulses, eight bits of data followed by an Acknowledge Bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, since a low-to-high transition
when the clock is high may be interpreted as a STOP signal.
The number of data bytes that can be transmitted over the
Rev. 0 | Page 14 of 24
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