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參數資料
| 型號： | ADT7461ARM-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | 【1∑C Temperature Monitor with Series Resistance Cancellation |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | MO-187-AA, MSOP-8 |
| 文件頁數： | 3/24頁 |
| 文件大小： | 854K |
| 代理商： | ADT7461ARM-REEL |
ADT7461
ADT7461–SPECIFICATIONS
Table 1. ADT7461 Specifications at T
A
= 40°C to +120°C , V
DD
= 3 V to 5.5 V, unless otherwise noted.
Parameter
Min
Typ
POWER SUPPLY
Supply Voltage, V
DD
3.0
3.30
Average Operating Supply Current, I
DD
170
5.5
5.5
Undervoltage Lockout Threshold
2.2
2.55
Power-On-Reset Threshold
1
TEMPERATURE-TO-DIGITAL CONVERTER
Local Sensor Accuracy
±1
Resolution
1
Remote Diode Sensor Accuracy
Resolution
0.25
Remote Sensor Source Current
96
36
6
Conversion Time
32.13
Max
5.5
215
10
20
2.8
2.5
±3
±1
±3
114.6
Unit
V
μA
μA
μA
V
V
°C
°C
°C
°C
°C
μA
μA
μA
ms
Test Conditions
0.0625 Conversions/Sec Rate
1
Standby Mode , –40°C ≤ T
A
≤ +85°C
Standby Mode, +85°C ≤ T
A
≤ +120°C
V
DD
Input, Disables ADC, Rising Edge
40°C ≤ T
A
≤ +100°C, 3 V ≤ V
DD
≤ 3.6 V
+60°C ≤ T
A
≤ +100°C, 55°C ≤ T
D 2
≤ +150°C, 3 V ≤ V
DD
≤ 3.6 V
40°C ≤ T
A
≤ +120°C, 55°C ≤ T
D 2
≤ +150°C, 3 V ≤ V
DD
≤ 5.5 V
High Level
3
Middle Level
3
Low Level
3
From Stop Bit to Conversion Complete (Both Channels) One-
Shot Mode with Averaging Switched On
One-Shot Mode with Averaging Off (i.e., Conversion Rate = 16,
32, or 64 Conversions per Second)
Resistance Split Evenly on Both the D+ and D– Inputs
3.2
12.56
ms
Maximum Series Resistance Cancelled
OPEN-DRAIN DIGITAL OUTPUTS
(THERM, ALERT/THERM2)
Output Low Voltage, V
OL
High Level Output Leakage Current, I
OH
ALERT Output Low Sink Current
SMBus INTERFACE
3, 4
Logic Input High Voltage, V
IH
SCLK, SDATA
Logic Input Low Voltage, V
IL
SCLK, SDATA
Hysteresis
SMBus Output Low Sink Current
Logic Input Current, I
IH
, I
IL
SMBus Input Capacitance, SCLK, SDATA
SMBus Clock Frequency
SMBus Timeout
5
SCLK Falling Edge to SDATA Valid Time
3
k
1
2.1
6
1
0.1
500
5
25
0.4
1
0.8
+1
400
64
1
V
μA
mA
V
V
mV
mA
μA
pF
kHz
ms
μs
I
OUT
= 6.0 mA
3
V
OUT
= V
DD
3
ALERT forced to 0.4 V
3 V ≤ V
DD
≤ 3.6 V
3 V ≤ V
DD
≤ 3.6 V
SDATA Forced to 0.6 V
User Programmable.
Master Clocking in Data
1
See Table 8 for information on other conversion rates.
2
Guaranteed by characterization but not production tested.
3
Guaranteed by design but not production tested.
4
See SMBus Timing Specifications section for more information.
5
Disabled by default. Details on how to enable it are in the SMBus section of this data sheet.
Rev. 0 | Page 3 of 24
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