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參數資料
型號: ADT7476AARQZ-R
廠商: ON Semiconductor
文件頁數: 38/66頁
文件大小: 945K
描述: IC REMOTE THERMAL CTLR 24QSOP
產品變化通告: MFG CHG Notification ADI to ON Semi
QSOP 24ld Pkg (MSL) Change 17/Jun/2010
標準包裝: 2,500
系列: dBCool®
功能: 風扇控制,溫度監控器
傳感器類型: 內部和外部
感應溫度: -40°C ~ 125°C
精確度: ±2.5%
拓撲: ADC,比較器,風扇速度計數器,多路復用器,寄存器庫
輸出類型: SMBus?
輸出警報:
輸出風扇:
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 24-QSOP
包裝: 帶卷 (TR)
其它名稱: ADT7476AARQZ-R-ND
ADT7476AARQZ-ROSTR
ADT7476A
http://onsemi.com
38
Step 4  PWM
MIN
 for Each PWM (Fan) Output
PWM
MIN
 is the minimum PWM duty cycle at which each
fan in the system runs. It is also the start speed for each fan
under automatic fan control once the temperature rises
above T
MIN
. For maximum system acoustic benefit,
PWM
MIN
 should be as low as possible. Depending on the
fan used, the PWM
MIN
 setting is usually in the 20% to 33%
duty cycle range. This value can be found through fan
validation.
Figure 54. PWM
MIN
 Determines Minimum
PWM Duty Cycle
T
MIN
100%
0%
TEMPERATURE
PWM
MIN
More than one PWM output can be controlled from a
single temperature measurement channel. For example,
Remote 1 temperature can control PWM1 and PWM2
outputs. If two different fans are used on PWM1 and PWM2,
the fan characteristics can be set up differently. As a result,
Fan 1 driven by PWM1 can have a different PWM
MIN
 value
than that of Fan 2 connected to PWM2. Figure 55 illustrates
this as PWM1
MIN
  (front fan), which is turned on at a
minimum duty cycle of 20%, while PWM2
MIN
 (rear fan)
turns on at a minimum of 40% duty cycle.
NOTE: Both fans turn on at exactly the same temperature, defined
by T
MIN
.
Figure 55. Operating Two Different Fans from
a Single Temperature Channel
T
MIN
100%
0%
TEMPERATURE
PWM1
MIN
PWM2
MIN
PWM1
PWM2
Programming the PWM Minimum Duty Cycle Registers
The PWM minimum duty cycle registers are 8-bit
registers that allow the minimum PWM duty cycle for each
output to be configured anywhere from 0% to 100%. This
allows the minimum PWM duty cycle to be set in steps of
0.39%.
The value to be programmed into the PWM
MIN
 register is
given by:
Value (decimal) = PWM
MIN
/0.39
Example 1:
For a minimum PWM duty cycle of 50%,
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 80 (hex)
Example 2:
For a minimum PWM duty cycle of 33%,
Value (decimal) = 33/0.39 = 85 (decimal)
Value = 85 (decimal) l or 54 (hex)
Table 45. PWM MINIMUM DUTY CYCLE REGISTERS
Register
Description
Default
0x64
PWM1 Minimum Duty Cycle
0x80 (50%)
0x65
PWM2 Minimum Duty Cycle
0x80 (50%)
0x66
PWM3 Minimum Duty Cycle
0x80 (50%)
Note on Fan Speed and PWM Duty Cycle
The PWM duty cycle does not directly correlate to fan
speed in RPM. Running a fan at 33% PWM duty cycle does
not equate to running the fan at 33% speed. Driving a fan at
33% PWM duty cycle actually runs the fan at closer to 50%
of its full speed. This is because fan speed in %RPM
generally relates to the square root of PWM duty cycle.
Given a PWM square wave as the drive signal, fan speed in
RPM approximates to:
%fanspeed +   PWM Duty Cycle 10
(eq. 5)
Step 5  PWM
MAX
 for PWM (Fan) Outputs
PWM
MAX
 is the maximum duty cycle that each fan in the
system runs at under the automatic fan speed control loop.
For maximum system acoustic benefit, PWM
MAX
 should be
as low as possible but should be capable of maintaining the
processor temperature limit at an acceptable level. If the
THERM
 temperature limit is exceeded, the fans are still
boosted to 100% for fail-safe cooling.
There is a PWM
MAX
 limit for each fan channel. The
default value of this register is 0xFF and has no effect unless
it is programmed.
Figure 56. PWM
MAX
 Determines Maximum PWM Duty
Cycle Below the THERM
 Temperature Limit
T
MIN
100%
0%
TEMPERATURE
PWM
MIN
PWM
MAX
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