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參數(shù)資料
| 型號(hào)： | ADT7519ARQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | SPI/I2C Compatible, Temperature Sensor, Four Channel ADC and Quad Voltage Output DAC |
| 中文描述： | DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 1Cel, RECTANGULAR, SURFACE MOUNT |
| 封裝： | MO-137AB, QSOP-16 |
| 文件頁數(shù)： | 6/44頁 |
| 文件大小： | 1350K |
| 代理商： | ADT7519ARQ |
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ADT7516/ADT7517/ADT7519
Parameter
1
POWER REQUIREMENTS
V
DD
V
DD
Settling Time
I
DD
(Normal Mode)
11
I
DD
(Power-Down Mode)
Power Dissipation
Rev. A | Page 6 of 44
Min
2.7
Typ
2.2
Max
5.5
50
3
3
10
10
10
33
Unit
V
ms
mA
mA
μA
μA
mW
μW
Conditions/Comments
V
DD
settles to within 10% of its final voltage level.
V
DD
= 3.3 V, V
IH
= V
DD
, and V
IL
= GND.
V
DD
= 5 V, V
IH
= V
DD
, and V
IL
= GND.
V
DD
= 3.3 V, V
IH
= V
DD
, and V
IL
= GND.
V
DD
= 5 V, V
IH
= V
DD
, and V
IL
= GND.
V
DD
= 3.3 V. Normal mode.
V
DD
= 3.3 V. Shutdown mode.
1
See the
2
DC specifications are tested with the outputs unloaded.
3
Linearity is tested using a reduced code range: ADT7516 (Code 115 to 4095); ADT7517 (Code 28 to 1023); ADT7519 (Code 8 to 255).
4
Guaranteed by design and characterization, not production tested.
5
Round robin is the continuous sequential measurement of the following channels: V
DD
, internal temperature, external temperature (AIN1, AIN2), AIN3, and AIN4.
6
For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage (V
REF
= V
DD
), the offset
plus gain error must be positive.
7
The SDA and SCL timing is measured with the input filters turned on to meet the fast-mode I
2
C specification. Switching off the input filters improves the transfer rate
but has a negative effect on the EMC behavior of the part.
8
Guaranteed by design, not production tested.
9
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
), and timed from a voltage level of 1.6 V.
10
Measured with the load circuit shown in Figure 4.
11
The I
DD
specification is valid for all DAC codes and full-scale analog input voltages. Interface inactive. All DACs and ADCs active. Load currents excluded.
section.
Terminology
DAC AC CHARACTERISTICS
Table 2. V
DD
= 2.7 V to 5.5 V, R
L
= 4.7 k to GND; C
L
= 200 pF to GND; 4.7 k to V
DD
; all specifications T
MIN
to T
MAX
, unless
otherwise noted.
Parameter
1, 2
Min
Typ
3
Max
Output Voltage Settling Time
ADT7519
6
8
ADT7517
7
9
ADT7516
8
10
Slew Rate
0.7
Major-Code Change Glitch Energy
12
Digital Feedthrough
0.5
Digital Crosstalk
1
Analog Crosstalk
0.5
DAC-to-DAC Crosstalk
3
Multiplying Bandwidth
200
Total Harmonic Distortion
–70
Unit
μs
μs
μs
V/μs
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
Conditions/Comments
V
REF
= V
DD
= 5 V.
1/4 scale to 3/4 scale change (40h to C0h).
1/4 scale to 3/4 scale change (100h to 300h).
1/4 scale to 3/4 scale change (400h to C00h).
1 LSB change around major carry.
V
REF
= 2 V ±0.1 V p-p.
V
REF
= 2.5 V ±0.1 V p-p. Frequency = 10 kHz.
1
See
2
Guaranteed by design and characterization, not production tested.
3
@ 25°C.
section.
Terminology
SCL
t
4
t
2
t
1
t
3
t
5
t
6
SDA
DATA IN
SDA
DATA OUT
0
Figure 2. I
2
C Bus Timing Diagram
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