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參數資料
| 型號： | ADUC814BRU-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Circular Connector; No. of Contacts:56; Series:LJT07R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:25-4 |
| 中文描述： | 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | 4.40 X 9.70 MM, MO-153AE, TSSOP-28 |
| 文件頁數： | 11/72頁 |
| 文件大小： | 846K |
| 代理商： | ADUC814BRU-REEL |
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ADuC814
Pin No.
17
18–21
Rev. A | Page 11 of 72
Mnemonic
C
REF
P1.4–P1.7
Type
I
I
Function
Decoupling Input for On-Chip Reference. Connect 0.1 μF between this pin and AGND.
Port 1.4 to P1.7. These pins have no digital output drivers, i.e., they can only function as digital inputs,
for which 0 must be written to the port bit. These port pins also have the following analog functionality:
ADC Input Channel 2. Selected via ADCCON2 SFR.
ADC Input Channel 2. Selected via ADCCON2 SFR.
ADC Input Channel 4. Selected via ADCCON2 SFR. The voltage DAC Channel 0 can also be configured
to appear on P1.6.
ADC Input Channel 5, selected via ADCCON2 SFR. The voltage DAC Channel 1 can also be configured
to appear on P1.7.
Bidirectional Port Pins with Internal Pull-Up Resistors. Port 3 pins that have 1s written to them are
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs
,with Port 3 pins being pulled low externally, they source current because of the internal pull-up
resistors. When driving a 0-to-1 output transition a strong pull-up is active during S1 of the instruction
cycle. Port 3 pins also have various secondary functions which are described as follows.
I/O Timer/Counter 1 Input. P3.5–P3.7 pins also have SPI interface functions. To enable these functions,
Bit 0 of the CFG814 SFR must be set to 1.
This pin also functions as the Slave Select input for the SPI interface when the device is operated in
slave mode. P3.5 can also function as an input for an external clock. This clock effectively bypasses the
PLL. This function is enabled by setting Bit 1 of the CFG814 SFR.
SPI Master Input/Slave Output Data Input/Output Pin.
SPI Master Output/Slave Input Data Input/Output Pin.
18
19
20
P1.4/ADC2
P1.5/ADC3
P1.6/ADC4/
DAC0
P1.7/
ADC5/DAC1
P3.5–P3.7
I
I
I/O
21
I/O
22–24
I/O
22
P3.5/T1
22
P3.5/SS
/EXTCLK
I/O
23
24
P3.6/MISO
P3.7/SDATA/
MOSI
SCLOCK
XTAL1
XTAL2
DV
DD
I/O
I/O
25
26
27
28
I = Input, O = Output, S = Supply, G - Ground.
I/O
I
O
S
Serial Clock Pin for SPI Serial Interface Clock.
Input to the Crystal Oscillator Inverter.
Output from the Crystal Oscillator Inverter.
Analog Positive Supply Voltage, 3 V or 5 V.
The following notes apply to the entire data sheet:
In bit designation tables,
set
implies a Logic 1 state, and
cleared
implies a Logic 0 state, unless otherwise stated.
Set
and
cleared
also imply that the bit is set or cleared by the ADuC814 hardware, unless otherwise stated.
User software should not write to reserved or unimplemented bits as they may be used in future products.
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| ADUC814BRU-REEL7 | Circular Connector; No. of Contacts:61; Series:LJT07R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:25-61 |
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