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| 型號(hào)： | ADUC841BCP8-3 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 10-823955-004 |
| 中文描述： | 8-BIT, FLASH, 8.38 MHz, MICROCONTROLLER, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FRAME, MO-220VLLD2, CSP-56 |
| 文件頁(yè)數(shù)： | 25/88頁(yè) |
| 文件大小： | 903K |
| 代理商： | ADUC841BCP8-3 |
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ADuC841/ADuC842/ADuC843
ADCCON2—(ADC Control SFR 2)
The ADCCON2 register controls ADC channel selection and
conversion modes as detailed below.
Rev. 0 | Page 25 of 88
SFR Address
SFR Power-On Default
Bit Addressable
Table 8. ADCCON2 SFR Bit Designations
Bit No.
Name
7
ADCI
D8H
00H
Yes
Description
ADC Interrupt Bit.
Set by hardware at the end of a single ADC conversion cycle or at the end of a DMA block conversion.
Cleared by hardware when the PC vectors to the ADC interrupt service routine. Otherwise, the ADCI bit is cleared
by user code.
DMA Mode Enable Bit.
Set by the user to enable a preconfigured ADC DMA mode operation. A more detailed description of this mode is
given in the ADC DMA Mode section. The DMA bit is automatically set to 0 at the end of a DMA cycle. Setting this
bit causes the ALE output to cease; it will start again when DMA is started and will operate correctly after DMA is
complete.
Continuous Conversion Bit.
Set by the user to initiate the ADC into a continuous mode of conversion. In this mode, the ADC starts converting
based on the timing and channel configuration already set up in the ADCCON SFRs; the ADC automatically starts
another conversion once a previous conversion has completed.
Single Conversion Bit.
Set to initiate a single conversion cycle. The SCONV bit is automatically reset to 0 on completion of the single
conversion cycle.
Channel Selection Bits.
Allow the user to program the ADC channel selection under software control. When a conversion is initiated, the
converted channel is the one pointed to by these channel selection bits. In DMA mode, the channel selection is
derived from the channel ID written to the external memory.
CS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
DMA STOP
6
DMA
5
CCONV
4
SCONV
3
2
1
0
CS3
CS2
CS1
CS0
CS2
0
0
0
0
1
1
1
1
0
0
0
0
1
CS1
0
0
1
1
0
0
1
1
0
0
1
1
0
CS0
0
1
0
1
0
1
0
1
0
1
0
1
0
CH#
0
1
2
3
4
5
6
7
Temp Monitor
DAC0
DAC1
AGND
V
REF
Requires minimum of 1 μs to acquire.
Only use with internal DAC output buffer on.
Only use with internal DAC output buffer on.
Place in XRAM location to finish DMA sequence; refer to
the ADC DMA Mode section.
All other combinations reserved.
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