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參數(shù)資料
| 型號： | ADUC842 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | CON, RTANG 68 POS |
| 中文描述： | 12 -位ADC和DAC的嵌入式高新技術(shù)高速62KB閃存微控制器 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大小： | 217K |
| 代理商： | ADUC842 |
Rev.PrB
ADuC842
I
2
C -C OMP A T IB L E INT E R F A C E
–14–
T he ADuC842 supports a fully licensed
*
I
2
C serial interface.
T he I
2
C interface is implemented as a full hardware slave
and software master. SDAT A is the data I/O pin and
SCLOCK is the serial clock. T hese two pins are shared with
the MOSI and SCLOCK pins of the on-chip SPI interface.
T o enable the I2C interface the SPI interface must be turned
off (see SPE in SPICON previously) OR the SPI interface
must be moved to P3.3, P3.4 and P3.5 via the CFG841.1
bit. Application Note uC001 describes the operation of this
interface as implemented is available from the
MicroConverter Website at www.analog.com/
microconverter.
T hree SFRs are used to control the I
2
C interface. T hese are described below:
I2C C ON:
SFR Address
Power-On Default Value
Bit Addressable
I
2
C Control Register
E 8H
00H
Y es
T able I2C C ON SF R Bit Designations Master Mode
Bit
Name
I
2
C Software Master Data Output Bit (MAST ER MODE ONL Y).
T his data bit is used to implement a master I
2
C transmitter interface in software. Data written
to this bit will be outputted on the SDAT A pin if the data output enable (MDE) bit is set.
I
2
C Software Master Data Output Enable Bit (MAST ER MODE ONL Y ).
Set
by user to enable the SDAT A pin as an output (T x).
Cleared
by the user to enable SDAT A pin as an input (Rx).
I
2
C Software Master Clock Output Bit (MAST ER MODE ONL Y ).
T his data bit is used to implement a master I
2
C transmitter interface in software. Data
written to this bit will be outputted on the SCLOCK pin.
I
2
C Software Master Data Input Bit (MAST ER MODE ONLY).
T his data bit is used to implement a master I
2
C receiver interface in software. Data on the
SDAT A pin is latched into this bit on SCLOCK if the Data Output Enable (MDE) bit is ‘0.’
I
2
C Master/Slave Mode Bit.
Set
by user to enable I
2
C software master mode.
Cleared
by user to enable I
2
C hardware slave mode.
R SV D
R SV D
R SV D
Description
7
M D O
6
M D E
5
M C O
4
M D I
3
I2C M
2
1
0
----
----
----
T able I2CCON SFR Bit Designations Slave Mode
Bit
Name
I
2
C Stop Interrupt Enable Bit.
Set by the user to enable I2C stop interrupts. If set a stop bit that follows a valid start
condition will generate an interrupt.
Cleared by the user to disable I2C stop interrupts.
I
2
C General Call Status Bit
Set
by hardware after receiving a general call address.
Cleared
by the user.
I
2
C Interrupt Decode Bits.
Set by hardware to indicate the source of an I2C interrupt
00 Start and Matching Address
01 Repeated Start and Matching Address
10 User Data
11 Stop after a Start and Matching Address
I
2
C Master/Slave Mode Bit.
Set
by user to enable I
2
C software master mode.
Cleared
by user to enable I
2
C hardware slave mode.
I
2
C Reset Bit (SL AVE MODE ONL Y ).
Set
by user to reset the I
2
C interface.
Cleared
by user code for normal I
2
C operation.
I
2
C Direction T ransfer Bit (SL AVE MODE ONL Y ).
Set
by the MicroConverter if the interface is transmitting.
D escription
7
I2C SI
6
I2C G C
5
4
I2C ID 1
I2C ID 0
3
I2C M
2
I2C RS
1
I2C T X
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