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參數資料

型號：	ADUC842BCP8-3
廠商：	ANALOG DEVICES INC
元件分類：	微控制器/微處理器
英文描述：	MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU
中文描述：	8-BIT, FLASH, 8.38 MHz, MICROCONTROLLER, QCC56
封裝：	8 X 8 MM, LEAD FRAME, MO-220VLLD2, CSP-56
文件頁數：	48/88頁
文件大?。?/td>	903K
代理商：	ADUC842BCP8-3

ADuC841/ADuC842/ADuC843

C COMPATIBLE INTERFACE

The ADuC841/ADuC842/ADuC843 support a fully licensed

C serial interface. The I

C interface is implemented as a full

hardware slave and software master. SDATA is the data I/O pin,

and SCLOCK is the serial clock. These two pins are shared with

the MOSI and SCLOCK pins of the on-chip SPI interface. To

enable the I

C interface, the SPI interface must be turned off

(see SPE in Table 18) or the SPI interface must be moved to

P3.3, P3.4, and P3.5 via the CFG841.1/CFG842.1 bit. Application

Note uC001 describes the operation of this interface as imple-

mented and is available from the MicroConverter website at

Table 19. I2CCON SFR Bit Designations, Master Mode

C Software Master Data Output Bit (Master Mode Only).

This data bit is used to implement a master I

C transmitter interface in software. Data written to this bit is output on

the SDATA pin if the data output enable (MDE) bit is set.

MDE

C Software Master Data Output Enable Bit (Master Mode Only).

Set by the user to enable the SDATA pin as an output (Tx).

Cleared by the user to enable the SDATA pin as an input (Rx).

MCO

C Software Master Clock Output Bit (Master Mode Only).

This data bit is used to implement a master I

C transmitter interface in software. Data written to this bit is output on

the SCLOCK pin.

MDI

C Software Master Data Input Bit (Master Mode Only).

This data bit is used to implement a master I

C receiver interface in software. Data on the SDATA pin is latched into

this bit on SCLOCK if the data output enable (MDE) bit is 0.

I2CM

C Master/Slave Mode Bit.

Set by the user to enable I

C software master mode.

Cleared by the user to enable I

C hardware slave mode.

Rev. 0 | Page 48 of 88

Three SFRs are used to control the I

C interface and are

described in the following tables.

Table 20. I2CCON SFR Bit Designations, Slave Mode

C Stop Interrupt Enable Bit.

Set by the user to enable I

C stop interrupts. If set, a stop bit that follows a valid start condition generates an

interrupt.

Cleared by the user to disable I

C stop interrupts.

I2CGC

C General Call Status Bit.

Set by hardware after receiving a general call address.

Cleared by the user.

I2CID1

C Interrupt Decode Bits.

I2CID0

Set by hardware to indicate the source of an I

C interrupt.

00 Start and Matching Address.

01 Repeated Start and Matching Address.

10 User Data.

11 Stop after a Start and Matching Address.

I2CM

C Master/Slave Mode Bit.

Set by the user to enable I

C software master mode.

Cleared by the user to enable I

C hardware slave mode.

相關PDF資料	PDF描述
ADUC843BCP8-3	MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU
ADUC842BCP8-5	MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU
ADUC843BCP8-5	MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU
ADUC841	MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU
ADUC841BCP62-3	MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU

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ADUC842BCPZ62-3	功能描述:IC ADC/DAC 12BIT W/MCU 56-LFCSP RoHS:是類別:集成電路 (IC) >> 嵌入式 - 微控制器，系列:MicroConverter® ADuC8xx 標準包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位速度:5MHz 連通性:IrDA，UART/USART 外圍設備:欠壓檢測/復位，LED，POR，PWM，WDT 輸入/輸出數:16 程序存儲器容量:4KB（4K x 8）程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數據轉換器:- 振蕩器型:內部工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬）包裝:管件其它名稱:269-4116Z8F0413SH005EG-ND
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