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| 型號： | ADUC842BS62-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU |
| 中文描述： | 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | PLASTIC, MO-112AC1, MQFP-52 |
| 文件頁數(shù)： | 48/88頁 |
| 文件大?。?/td> | 903K |
| 代理商： | ADUC842BS62-5 |
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ADuC841/ADuC842/ADuC843
I
2
C COMPATIBLE INTERFACE
The ADuC841/ADuC842/ADuC843 support a fully licensed
I
2
C serial interface. The I
2
C interface is implemented as a full
hardware slave and software master. SDATA is the data I/O pin,
and SCLOCK is the serial clock. These two pins are shared with
the MOSI and SCLOCK pins of the on-chip SPI interface. To
enable the I
2
C interface, the SPI interface must be turned off
(see SPE in Table 18) or the SPI interface must be moved to
P3.3, P3.4, and P3.5 via the CFG841.1/CFG842.1 bit. Application
Note uC001 describes the operation of this interface as imple-
mented and is available from the MicroConverter website at
. Table 19. I2CCON SFR Bit Designations, Master Mode
Bit No.
Name
Description
7
MDO
I
2
C Software Master Data Output Bit (Master Mode Only).
This data bit is used to implement a master I
2
C transmitter interface in software. Data written to this bit is output on
the SDATA pin if the data output enable (MDE) bit is set.
6
MDE
I
2
C Software Master Data Output Enable Bit (Master Mode Only).
Set by the user to enable the SDATA pin as an output (Tx).
Cleared by the user to enable the SDATA pin as an input (Rx).
5
MCO
I
2
C Software Master Clock Output Bit (Master Mode Only).
This data bit is used to implement a master I
2
C transmitter interface in software. Data written to this bit is output on
the SCLOCK pin.
4
MDI
I
2
C Software Master Data Input Bit (Master Mode Only).
This data bit is used to implement a master I
2
C receiver interface in software. Data on the SDATA pin is latched into
this bit on SCLOCK if the data output enable (MDE) bit is 0.
3
I2CM
I
2
C Master/Slave Mode Bit.
Set by the user to enable I
2
C software master mode.
Cleared by the user to enable I
2
C hardware slave mode.
2
----
Reserved.
1
----
Reserved.
0
----
Reserved.
Rev. 0 | Page 48 of 88
Three SFRs are used to control the I
2
C interface and are
described in the following tables.
I2CCON
SFR Address
Power-On Default
Bit Addressable
I
2
C Control Register
E8H
00H
Yes
Table 20. I2CCON SFR Bit Designations, Slave Mode
Bit No.
Name
Description
7
I2CSI
I
2
C Stop Interrupt Enable Bit.
Set by the user to enable I
2
C stop interrupts. If set, a stop bit that follows a valid start condition generates an
interrupt.
Cleared by the user to disable I
2
C stop interrupts.
6
I2CGC
I
2
C General Call Status Bit.
Set by hardware after receiving a general call address.
Cleared by the user.
5
I2CID1
I
2
C Interrupt Decode Bits.
4
I2CID0
Set by hardware to indicate the source of an I
2
C interrupt.
00 Start and Matching Address.
01 Repeated Start and Matching Address.
10 User Data.
11 Stop after a Start and Matching Address.
3
I2CM
I
2
C Master/Slave Mode Bit.
Set by the user to enable I
2
C software master mode.
Cleared by the user to enable I
2
C hardware slave mode.
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參數(shù)描述 |
|---|---|
| ADUC842BSZ62-3 | 功能描述:IC ADC/DAC 12BIT W/MCU 52MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標(biāo)準(zhǔn)包裝:250 系列:LPC11Uxx 核心處理器:ARM? Cortex?-M0 芯體尺寸:32-位 速度:50MHz 連通性:I²C，Microwire，SPI，SSI，SSP，UART/USART，USB 外圍設(shè)備:欠壓檢測/復(fù)位，POR，WDT 輸入/輸出數(shù):40 程序存儲器容量:96KB（96K x 8） 程序存儲器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):1.8 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-LQFP 包裝:托盤 其它名稱:568-9587 |
| ADUC842BSZ62-3 | 制造商:Analog Devices 功能描述:IC MICROCONTROLLER |
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| ADUC842BSZ62-5 | 制造商:Analog Devices 功能描述:IC MICROCONTROLLER |
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