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參數資料
| 型號： | ADUC843BS62-3 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU |
| 中文描述： | 8-BIT, FLASH, 8.38 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | PLASTIC, MO-112AC1, MQFP-52 |
| 文件頁數： | 41/88頁 |
| 文件大小： | 903K |
| 代理商： | ADUC843BS62-3 |
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ADuC841/ADuC842/ADuC843
ON-CHIP PLL
The ADuC842 and ADuC843 are intended for use with a
32.768 kHz watch crystal. A PLL locks onto a multiple (512) of
this to provide a stable 16.78 MHz clock for the system. The
ADuC841 operates directly from an external crystal. The core
can operate at this frequency or at binary submultiples of it to
allow power saving in cases where maximum core performance
is not required. The default core clock is the PLL clock divided
by 8 or 2.097152 MHz. The ADC clocks are also derived from
the PLL clock, with the modulator rate being the same as the
crystal oscillator frequency. The preceding choice of frequencies
ensures that the modulators and the core are synchronous,
regardless of the core clock rate. The PLL control register is
PLLCON.
Rev. 0 | Page 41 of 88
At 5 V the core clock can be set to a maximum of 16.78 MHz,
while at 3 V the maximum core clock setting is 8.38 MHz. The
CD bits should not be set to 0 on a 3 V part.
Note that on the ADuC841, changing the CD bits in PLLCON
causes the core speed to change. The core speed is crystal freq/
2
CD
. The other bits in PLLCON are reserved in the case of the
ADuC841 and should be written with 0.
PLLCON PLL
SFR Address
Power-On Default
Bit Addressable
Control Register
D7H
53H
No
Table 16. PLLCON SFR Bit Designations
Bit No.
Name
7
OSC_PD
Description
Oscillator Power-Down Bit.
Set by the user to halt the 32 kHz oscillator in power-down mode.
Cleared by the user to enable the 32 kHz oscillator in power-down mode.
This feature allows the TIC to continue counting even in power-down mode.
PLL Lock Bit.
This is a read-only bit.
Set automatically at power-on to indicate that the PLL loop is correctly tracking the crystal clock. If the external
crystal subsequently becomes disconnected, the PLL will rail.
Cleared automatically at power-on to indicate that the PLL is not correctly tracking the crystal clock. This may be due
to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output can be 16.78 MHz
±20%.
Reserved. Should be written with 0.
Reserved. Should be written with 0.
Fast Interrupt Response Bit.
Set by the user enabling the response to any interrupt to be executed at the fastest core clock frequency, regardless
of the configuration of the CD2–0 bits (see below). Once user code has returned from an interrupt, the core resumes
code execution at the core clock selected by the CD2–0 bits.
Cleared by the user to disable the fast interrupt response feature.
CPU (Core Clock) Divider Bits.
This number determines the frequency at which the microcontroller core operates.
CD2
0
0
0
0
1
1
1
1
1
1
0.131072
6
LOCK
5
4
3
----
----
FINT
2
1
0
CD2
CD1
CD0
CD1
0
0
1
1
0
0
1
CD0
0
1
0
1
0
1
0
Core Clock Frequency (MHz)
16.777216
8.388608
4.194304
2.097152 (Default Core Clock Frequency)
1.048576
0.524288
0.262144
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相關代理商/技術參數 |
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| ADUC843BSZ62-3 | 功能描述:IC ADC 12BIT W/FLASH MCU 52-MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標準包裝:250 系列:LPC11Uxx 核心處理器:ARM? Cortex?-M0 芯體尺寸:32-位 速度:50MHz 連通性:I²C，Microwire，SPI，SSI，SSP，UART/USART，USB 外圍設備:欠壓檢測/復位，POR，WDT 輸入/輸出數:40 程序存儲器容量:96KB（96K x 8） 程序存儲器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):1.8 V ~ 3.6 V 數據轉換器:A/D 8x10b 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-LQFP 包裝:托盤 其它名稱:568-9587 |
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| ADUC844BCP32-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter, Dual 16-Bit/24-Bit ADCs with Embedded 62kB FLASH MCU |
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