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參數資料
| 型號： | ADUC846BCP8-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, Dual 16-Bit ADCs with Embedded 62kB FLASH MCU |
| 中文描述： | 16-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56 |
| 封裝： | 8 X 8 MM, LFCSP-56 |
| 文件頁數： | 9/20頁 |
| 文件大小： | 1984K |
| 代理商： | ADUC846BCP8-5 |
ADuC846
PRELIMINARY TECHNICAL DATA
PIN FUNCTION DESCRIPTIONS
Pin No:
52-MQFP
1, 2
Pin No:
56-CSP
56, 1
Pin
Mnemonic
P1.0/P1.1
Type*
Description
P1.0 and P1.1 can function as a digital inputs or digital outputs and have a pull-
up configuration as described below for Port 3. P1.0 and P1.1 have an increased
current drive sink capability of 10mA.
P1.0 and P1.1 also have various secondary functions as described below.
P1.0 can also be used to provide a clock input to Timer 2. When enabled,
counter 2 is incremented in response to a negative transition on the T2 input
pin.
If the PWM is enabled, the PWM0 output will appear at this pin.
P1.1 can also be used to provide a control input to Timer 2. When enabled, a
negative transition on the T2EX input pin will cause a Timer 2 capture or reload
event.
If the PWM is enabled, the PWM1 output will appear at this pin.
Port 1.2 to Port 1.7 have no digital output driver; they can function as a digital
input for which ‘0’ must be written to the port bit. As a digital input, these pins
must be driven high or low externally.
These pins also have the following analog functionality:
The voltage output from the DAC or one or both current sources (200uA or 2 x
200uA) can be configured to appear at this pin.
Auxiliary ADC Input or one or both current sources can be configured at this
pin.
Primary ADC, Positive Analog Input
I/O
P1.0/T2/PWM0
I/O
P1.1/T2EX/PWM1
I/O
3
4
9
12
2
3
11
14
P1.2
P1.7
I
P1.2/DAC/IEXC1
I/O
P1.3/AIN5/IEXC2
I/O
P1.4/AIN1
I
P1.5/AIN2
I
Primary ADC, Negative Analog Input
P1.6/AIN3
I
Auxiliary ADC Input or Muxed Primary ADC, Positive Analog Input
P1.7/AIN4/DAC
I/O
Auxiliary ADC Input or Muxed Primary ADC, Negative Analog Input. The
voltage
Analog Supply Voltage
5
4
AVDD
S
6
5
AGND
S
Analog Ground.
N/C
6
AGND
S
A second Analog ground is provided with the CSP version only.
7
7
REFIN-
I
External Reference Input, negative terminal
8
8
REFIN+
I
External Reference Input, positive terminal
13
15
SS
I
The slave select input for the SPI Interface is present at this pin. A weak pull-up
is present on this pin.
Master Input/Slave Output for the SPI Interface. There is a weak pull-up on this
input pin.
Reset Input. A high level on this pin for 16 core clock cycles while the
oscillator is running resets the device. There is an internal weak pull-down and
a Schmitt trigger input stage on this pin.
14
16
MISO
I
15
17
RESET
I
REV. PrA
-9-
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