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參數(shù)資料
型號(hào): ADUM1300CRWZ
廠商: ANALOG DEVICES INC
元件分類: 模擬信號(hào)調(diào)理
英文描述: Triple-Channel Digital Isolators
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO16
封裝: ROHS COMPLIANT, MS-013AA, SOIC-16
文件頁(yè)數(shù): 17/20頁(yè)
文件大小: 713K
代理商: ADUM1300CRWZ
ADuM1300/ADuM1301
Rev. C | Page 17 of 20
MAGNETIC FIELD FREQUENCY (Hz)
100.000
M
D
0.001
1M
10.000
0.010
1k
10k
10M
0.100
1.000
100M
100k
0
Figure 16. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and was of the worst-case polarity), it would reduce the
received pulse from > 1.0 V to 0.75 V—still well above the 0.5 V
sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM130x transformers. Figure 17 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As seen, the ADuM130x is extremely immune and
can be affected only by extremely large currents operated at
high frequency, very close to the component. For the 1 MHz
example, one would have to place a 0.5 kA current 5 mm away
from the ADuM130x to affect the component’s operation.
MAGNETIC FIELD FREQUENCY (Hz)
M
1000.00
100.00
10.00
1.00
0.10
0.01
1k
10k
100M
100k
1M
10M
DISTANCE = 5mm
DISTANCE = 1m
DISTANCE = 100mm
0
Figure 17. Maximum Allowable Current
for Various Current-to-ADuM130x Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce sufficiently large error voltages to trigger the
thresholds of succeeding circuitry. Care should be taken in
the layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM130x isola-
tor is a function of the supply voltage, the channel’s data rate,
and the channel’s output load.
For each input channel, the supply current is given by
I
DDI
= I
DDI
(
Q
)
f
≤ 0.5
f
r
I
DDI
= I
DDI
(
D
)
× (2
f – f
r
) +
I
DDI (Q)
f > 0.5
f
r
For each output channel, the supply current is given by
I
DDO
= I
DDO
(
Q
)
f
≤ 0.5
f
r
I
DDO
= (
I
DDO
(
D
)
+ (0.5 × 10
3
) ×
C
L
V
DDO
) × (2
f – f
r
) +
I
DDO
(
Q
)
f
> 0.5
f
r
where:
I
DDI
(
D
)
,
I
DDO
(
D
)
are the input and output dynamic supply currents
per channel (mA/Mbps).
C
L
is output load capacitance (pF).
V
DDO
is the output supply voltage (V).
f
is the input logic signal frequency (MHz, half of the input data
rate, NRZ signaling).
f
r
is the input stage refresh rate (Mbps).
I
DDI
(
Q
)
,
I
DDO
(
Q
)
are the specified input and output quiescent sup-
ply currents (mA).
To calculate the total I
DD1
and I
DD2
supply current, the supply
currents for each input and output channel corresponding to
I
DD1
and I
DD2
are calculated and totaled. Figure 6 and Figure 7
provide per-channel supply currents as a function of data rate
for an unloaded output condition. Figure 8 provides per-
channel supply current as a function of data rate for a 15 pF
output condition. Figure 9 through Figure 12 provide total
I
DD1
and I
DD2
supply current as a function of data rate for
ADuM1300/ADuM1301 channel configurations.
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