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參數(shù)資料
| 型號： | ADUM1411BRWZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | Quad-Channel Digital Isolators |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PDSO16 |
| 封裝： | ROHS COMPLIANT, MS-013AA, SOIC-16 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 277K |
| 代理商： | ADUM1411BRWZ-RL |
ADuM1410/ADuM1411/ADuM1412
Parameter
ADuM141xBRW
Minimum Pulse Width
3
Maximum Data Rate
4
Propagation Delay
5
Pulse Width Distortion, |t
PLH
t
PHL
|
5
Change vs. Temperature
Propagation Delay Skew
6
Channel-to-Channel Matching,
Codirectional Channels
7
Channel-to-Channel Matching,
Opposing-Directional Channels
7
For All Models
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output
8
Common-Mode Transient Immunity
at Logic Low Output
8
Refresh Rate
Input Enable Time
9
Input Disable Time
9
Input Dynamic Supply Current per
Channel
10
Output Dynamic Supply Current per
Channel
10
1
All voltages are relative to their respective ground.
2
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total V
DD1
and V
DD2
supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
6
t
PSK
is the magnitude of the worst-case difference in t
PHL
or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Input enable time is the duration from when V
DISABLE
is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V
DISABLE
is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL logic state (See Table 10).
10
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. E | Page 4 of 20
Symbol
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
Min
10
20
Typ
30
5
Max
100
50
5
30
5
Unit
ns
Mbps
ns
ns
ps/°C
ns
ns
Test Conditions
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
t
PSKOD
6
ns
C
L
= 15 pF, CMOS signal levels
t
R
/t
F
|CM
H
|
25
2.5
35
ns
kV/μs
C
L
= 15 pF, CMOS signal levels
V
Ix
= V
DD1
/V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
V
IA
, V
IB
, V
IC
, V
ID
, = 0 or V
DD1
V
IA
, V
IB
, V
IC
, V
ID
, = 0 or V
DD1
|CM
L
|
25
35
kV/μs
f
r
t
ENABLE
t
DISABLE
I
DDI (D)
1.2
0.12
2.0
5.0
Mbps
μs
μs
mA/Mbps
I
DDO (D)
0.04
mA/Mbps
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADUM1412 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-Channel Digital Isolators |
| ADUM1412ARWZ | 功能描述:IC ISOLATOR DGTL QUAD 16-SOIC RoHS:是 類別:隔離器 >> 數(shù)字隔離器 系列:iCoupler® 標(biāo)準(zhǔn)包裝:66 系列:iCoupler® 輸入 - 1 側(cè)/2 側(cè):2/2 通道數(shù):4 電源電壓:3.3V，5V 電壓 - 隔離:2500Vrms 數(shù)據(jù)速率:25Mbps 傳輸延遲:60ns 輸出類型:邏輯 封裝/外殼:20-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:20-SSOP 包裝:管件 工作溫度:-40°C ~ 105°C |
| ADUM1412ARWZ-RL | 功能描述:IC ISOLATOR DGTL QUAD 16-SOIC RoHS:是 類別:隔離器 >> 數(shù)字隔離器 系列:iCoupler® 產(chǎn)品培訓(xùn)模塊:IsoLoop® Isolator 標(biāo)準(zhǔn)包裝:50 系列:IsoLoop® 輸入 - 1 側(cè)/2 側(cè):5/0 通道數(shù):5 電源電壓:3 V ~ 5.5 V 電壓 - 隔離:2500Vrms 數(shù)據(jù)速率:110Mbps 傳輸延遲:12ns 輸出類型:CMOS 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC N 包裝:管件 工作溫度:-40°C ~ 85°C 其它名稱:390-1053-5 |
| ADUM1412BRWZ | 功能描述:IC ISOLATOR DGTL QUAD 16-SOIC RoHS:是 類別:隔離器 >> 數(shù)字隔離器 系列:iCoupler® 標(biāo)準(zhǔn)包裝:66 系列:iCoupler® 輸入 - 1 側(cè)/2 側(cè):2/2 通道數(shù):4 電源電壓:3.3V，5V 電壓 - 隔離:2500Vrms 數(shù)據(jù)速率:25Mbps 傳輸延遲:60ns 輸出類型:邏輯 封裝/外殼:20-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:20-SSOP 包裝:管件 工作溫度:-40°C ~ 105°C |
| ADUM1412BRWZ | 制造商:Analog Devices 功能描述:DIGITAL ISOLATOR, 4CH, 30NS, WSOIC-16 |
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